The information is transferred byte-wise and each receiv-
er acknowledges with a ninth bit.
Within the bus specifications a standard mode (100kHz
clock rate) and a fast mode (400kHz clock rate) are
defined. The DS1624 works in both modes.
Acknowledge: Each receiving device, when addressed,
is obliged to generate an acknowledge after the reception
of each byte. The master device must generate an extra
clock pulse, which is associated with this acknowledge bit.
A device that acknowledges must pull down the SDA line
during the acknowledge clock pulse in such a way that
the SDA line is stable low during the high period of the
acknowledge related clock pulse. Of course, setup and
hold times must be taken into account. A master must
signal an end of data to the slave by not generating an
acknowledge bit on the last byte that has been clocked
out of the slave. In this case, the slave must leave the
data line high to enable the master to generate the STOP
condition.
Figure 2 details how data transfer is accomplished on the
two-wire bus. Depending upon the state of the R/W bit,
two types of data transfer are possible:
1. Data transfer from a master transmitter to a slave
receiver. The first byte transmitted by the master
is the slave address. Next follows a number of data
bytes. The slave returns an acknowledge bit after each
received byte.
2. Data transfer from a slave transmitter to a master
receiver. The first byte (the slave address) is transmit-
ted by the master. The slave then returns an acknowl-
edge bit. Next follows a number of data bytes transmit-
ted by the slave to the master. The master returns an
acknowledge bit after all received bytes other than the
last byte. At the end of the last received byte, a ‘not
acknowledge’ is returned.
The master device generates all of the serial clock pulses
and the START and STOP conditions. A transfer is ended
with a STOP condition or with a repeated START condi-
tion. Since a repeated START condition is also the begin-
ning of the next serial transfer, the bus is not released.
The DS1624 can operate in the following two modes:
1. Slave receiver mode: Serial data and clock are
received through SDA and SCL. After each byte is
received an acknowledge bit is transmitted. START
and STOP conditions are recognized as the begin-
ning and end of a serial transfer. Address recognition
is performed by hardware after reception of the slave
address and direction bit.
2. Slave transmitter mode: The first byte is received
and handled as in the slave receiver mode. However,
in this mode the direction bit indicates that the transfer
direction is reversed. Serial data is transmitted on SDA
by the DS1624 while the serial clock is input on SCL.
START and STOP conditions are recognized as the
beginning and end of a serial transfer.
Figure 2. Data Transfer on 2-Wire Serial Bus
SDA
SCL
START
CONDITION
MSB
SLAVE ADDRESS
R/W
DIRECTION BIT
ACKNOWLEDGEMENT
SIGNAL FROM RECEIVER
ACKNOWLEDGEMENT
SIGNAL FROM RECEIVER
1 2 6 7 8 9
ACK
REPEATED IF MORE BYTES
ARE TRANSFERRED
1 2 3-8 8 9
STOP CONDITION
OR
REPEATED
START CONDITION
ACK
DS1624 Digital Thermometer and Memory
www.maximintegrated.com
Maxim Integrated
│
6
