Figure 4. Current Transfer Ratio vs. Temperature. Figure 5. Logic High Output Current vs. Temperature.
Figure 1. DC and Pulsed Transfer Characteristics. Figure 2. Current Transfer Ratio vs. Input Current. Figure 3. Input Current vs. Forward Voltage.
Notes:
1. Derate linearly above 70°C free-air temperature at a rate of 0.8 mA/°C.
2. Derate linearly above 70°C free-air temperature at a rate of 1.6mA/°C.
3. Derate linearly above 70°C free-air temperature at a rate of 0.9 mA/°C.
4. Derate linearly above 70°C free-air temperature at a rate of 2.0 mA/°C.
5. CURRENT TRANSFER RATIO in percent is dened as the ratio of output collector current (I
O
), to the forward LED input current (I
F
), times 100.
6. Device considered a two-terminal device: Pins 1 and 3 shorted together and Pins 4, 5 and 6 shorted together.
7. Under TTL load and drive conditions: Common mode transient immunity in a Logic High level is the maximum tolerable (positive) dV
CM
/dt on
the leading edge of the common mode pulse, V
CM
, to assure that the output will remain in a Logic High state (i.e., V
O
> 2.0 V). Common mode
transient immunity in a Logic Low level is the maximum tolerable (negative) dV
CM
/dt on the trailing edge of the common mode pulse signal,
V
CM
, to assure that the output will remain in a Logic Low state (i.e., V
O
< 0.8 V).
8. Under IPM (Intelligent Power Module) load and LED drive conditions: Common mode transient immunity in a Logic High level is the maxi-
mum tolerable dV
CM
/dt on the leading edge of the common mode pulse, V
CM
, to assure that the output will remain in a Logic High state (i.e.,
V
O
> 3.0 V). Common mode transient immunity in a Logic Low level is the maximum tolerable dV
CM
/dt on the trailing edge of the common
mode pulse signal,V
CM
, to assure that the output will remain in a Logic Low state (i.e., V
O
< 1.0 V).
9. The 1.9 kΩ load represents 1 TTL unit load of 1.6 mA and the 5.6 kΩ pull-up resistor.
10. The R
L
= 20 kΩ, C
L
= 100 pF load represents an IPM (Intelligent Power Mode) load.
11. Use of a 0.1 µF bypass capacitor connected between pins 4 and 6 is recommended.
12. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥4500 V
RMS
for 1 second (leakage detec-
tion current limit, I
i-e
≤ 5 µA).
13. The dierence between t
PLH
and t
PHL
, between any two HCPL-M454 parts under the same test condition. (See Power Inverter Dead Time and
Propagation Delay Specications section).
HCPL-M454 fig 1
0
10
20
V
O
– OUTPUT VOLTAGE – V
I
O
– OUTPUT CURRENT – mA
10
5
0
T = 25°C
V = 5.0 V
A
CC
40 mA
35 mA
30 mA
25 mA
20 mA
15 mA
10 mA
I = 5 mA
F
I
F
– INPUT CURRENT – mA
NORMALIZED CURRENT TRANSFER RATIO
1.5
1.0
0.5
0.0
2 4 6 8 10 12 14 16
18
0
HCPL-M454 fig 2
20
22
24 26
I
F
= 16 mA
V
O
= 0.4 V
V
CC
= 5.0 V
T
A
= 25°C
NORMALIZED
HCPL-M454 fig 3
V
F
– FORWARD VOLTAGE – VOLTS
100
10
0.1
0.01
1.1 1.2 1.3 1.4
I
F
– FORWARD CURRENT – mA
1.61.5
1.0
0.001
1000
I
F
V
F
+
T = 25°C
A
–
T
A
– TEMPERATURE – °C
NORMALIZED CURRENT TRANSFER RATIO
1.0
0.8
0.6
HCPL-M454 fig 4
1.1
0.7
0.9
-40
-20
0
20
40 60 80 100 120-60
I
F
= 16 mA
V
O
= 0.4 V
V
CC
= 5.0 V
T
A
= 25°C
NORMALIZED
T
A
– TEMPERATURE – °C
I
OH
– LOGIC HIGH OUTPUT CURRENT – nA
HCPL-M454 fig 5
10
4
10
3
10
2
10
1
10
0
10
-1
10
-2
-40 -20 0 20 40 60 80 100
120
-60
I
F
= 0 mA
V
O
= V
CC
= 5.0 V
