AMIS−42770
http://onsemi.com
7
Feedback Suppression
The logic unit described in Table 3 constantly ensures that
dominant symbols on one bus line are transmitted to the
other bus line without imposing any priority on either of the
lines. This feature would lead to an “interlock” state with
permanent dominant signal transmitted to both bus lines, if
no extra measure is taken.
Therefore feedback suppression is included inside the
logic unit of the transceiver. This block masks−out reception
on that bus line, on which a dominant is actively transmitted.
The reception becomes active again only with certain delay
after the dominant transmission on this line is finished.
Power−on−Reset (POR)
While Vcc voltage is below the POR level, the POR
circuit makes sure that:
• The counters are kept in the reset mode and stable state
without current consumption
• Inputs are disabled (don’t care)
• Outputs are high impedant; only Rx0 = high−level
• Analog blocks are in power down
• Oscillator not running and in power down
• CANHx and CANLx are recessive
• VREF output high impedant for POR not released
Over Temperature Detection
A thermal protection circuit is integrated to prevent the
transceiver from damage if the junction temperature
exceeds thermal shutdown level. Because the transmitters
dissipate most of the total power, the transmitters will be
switched off only to reduce power dissipation and IC
temperature. All other IC functions continue to operate.
Fault Behavior
A fault like a short circuit is limited to that bus line where
it occurs; hence data interchange from the protocol IC to the
other bus system is not affected.
When the voltage at the bus lines is going out of the normal
operating range (−12 V to +12 V), the receiver is not allowed
to erroneously detect a dominant state.
Short Circuits
A current−limiting circuit protects the transmitter output
stage from damage caused by an accidental short−circuit to
either positive or negative supply voltage, although power
dissipation increases during this fault condition.
The pins CANHx and CANLx are protected from
automotive electrical transients (according to “ISO 7637”).
ELECTRICAL CHARACTERISTICS
Definitions
All voltages are referenced to GND. Positive currents
flow into the IC. Sinking current means that the current is
flowing into the pin. Sourcing current means that the current
is flowing out of the pin.
Table 4. ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Conditions Min. Max. Unit
V
CC
Supply voltage −0.3 +7 V
V
CANHx
DC voltage at pin CANH1/2 0 < V
CC
< 5.25 V; no time limit −45 +45 V
V
CANLx
DC voltage at pin CANL1/2 0 < V
CC
< 5.25 V; no time limit −45 +45 V
V
digIO
DC voltage at digital IO pins (EN1B, EN2B,
Rint, Rx0, Text, Tx0)
−0.3 V
CC
+ 0.3 V
V
REF
DC voltage at pin V
REF
−0.3 V
CC
+ 0.3 V
V
tran(CANHx)
Transient voltage at pin CANH1/2 (Note 4) −150 +150 V
V
tran(CANLx)
Transient voltage at pin CANL1/2 (Note 4) −150 +150 V
V
esd(CANLx/CANHx)
ESD voltage at CANH1/2 and CANL1/2 pins (Note 5)
(Note 7)
−4
−500
+4
+500
kV
V
V
esd
ESD voltage at all other pins (Note 5)
(Note 7)
−2
−250
+2
+250
kV
V
Latch−up Static latch−up at all pins (Note 6) 100 mA
T
stg
Storage temperature −55 +155 °C
T
amb
Ambient temperature −40 +125 °C
T
junc
Maximum junction temperature −40 +150 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
4. Applied transient waveforms in accordance with “ISO 7637 part 3”, test pulses 1, 2, 3a, and 3b (see Figure 6)
5. Standardized human body model (HBM) ESD pulses in accordance to MIL883 method 3015. Supply pin 8 is ±2 kV.
6. Static latch−up immunity: static latch−up protection level when tested according to EIA/JESD78.
7. Standardized charged device model ESD pulses when tested according to EOS/ESD DS5.3−1993.
