CY7C037-15AC Datasheet CY7C028-15AC, CY7C037-15AC | P1-P3

32K/64K x 16/18

Dual-Port Static RAM

CY7C027/028

CY7C037/038

Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600

Document #: 38-06042 Rev. *A Revised December 27, 2002

25/0251

Features

• True Dual-Ported memory cells which allow simulta-

neous access of the same memory location

• 32K x 16 organization (CY7C027)

• 64K x 16 organization (CY7C028)

• 32K x 18 organization (CY7C037)

• 64K x 18 organization (CY7C038)

• 0.35-micron CMOS for optimum speed/power

• High-speed access: 12

[1]

/15/20 ns

• Low operating power

— Active: I

CC

= 180 mA (typical)

— Standby: I

SB3

= 0.05 mA (typical)

• Fully asynchronous operation

• Automatic power-down

• Expandable data bus to 32/36 bits or more using Mas-

ter/Slave chip select when using more than one device

• On-chip arbitration logic

• Semaphores included to permit software handshaking

between ports

• INT

flags for port-to-port communication

• Separate upper-byte and lower-byte control

• Dual Chip Enables

• Pin select for Master or Slave

• Commercial and industrial temperature ranges

• Available in 100-pin TQFP

• Pin-compatible and functionally equivalent to IDT7027

Notes:

1. See page 6 for Load Conditions.

2. I/O

8

–I/O

15

for x16 devices; I/O

9

–I/O

17

for x18 devices.

3. I/O

0

–I/O

7

for x16 devices; I/O

0

–I/O

8

for x18 devices.

4. A

0

–A

14

for 32K; A

0

–A

15

for 64K devices.

5. BUSY

is an output in master mode and an input in slave mode.

R/W

L

CE

0L

CE

1L

OE

L

I/O

8/9L

–I/O

15/17L

I/O

Control

Address

Decode

A

0L

–A

14/15L

CE

L

OE

L

R/W

L

BUSY

L

I/O

Control

CE

L

Interrupt

Semaphore

Arbitration

SEM

L

INT

L

M/S

UB

L

LB

L

I/O

0L

–I/O

7/8L

R/W

R

CE

0R

CE

1R

OE

R

I/O

8/9L

–I/O

15/17R

CE

R

UB

R

LB

R

I/O

0L

–I/O

7/8R

UB

L

LB

L

Logic Block Diagram

A

0L

–A

14/15L

True Dual-Ported

RAM Array

A

0R

–A

14/15R

CE

R

OE

R

R/W

R

BUSY

R

SEM

R

INT

R

UB

R

LB

R

Address

Decode

A

0R

–A

14/15R

[2]

[3]

[4]

[5]

[4] [4]

15/16

8/9

15/16

8/9

15/16 15/16

For the most recent information, visit the Cypress web site at www.cypress.com

CY7C027/028

CY7C037/038

Document #: 38-06042 Rev. *A Page 2 of 19

Functional Description

The CY7C027/028 and CY7C037/038 are low-power CMOS

32K, 64K x 16/18 dual-port static RAMs. Various arbitration

schemes are included on the devices to handle situations

when multiple processors access the same piece of data. Two

ports are provided, permitting independent, asynchronous ac-

cess for reads and writes to any location in memory. The de-

vices can be utilized as standalone 16/18-bit dual-port static

RAMs or multiple devices can be combined in order to function

as a 32/36-bit or wider master/slave dual-port static RAM. An

M/S

pin is provided for implementing 32/36-bit or wider mem-

ory applications without the need for separate master and

slave devices or additional discrete logic. Application areas

include interprocessor/multiprocessor designs, communica-

tions status buffering, and dual-port video/graphics memory.

Each port has independent control pins: dual chip enables

(CE

0

and CE

1

), read or write enable (R/W), and output enable

(OE). Two flags are provided on each port (BUSY and INT). BUSY

signals that the port is trying to access the same location currently

being accessed by the other port. The interrupt flag (INT

) permits

communication between ports or systems by means of a mail box.

The semaphores are used to pass a flag, or token, from one port to

the other to indicate that a shared resource is in use. The semaphore

logic is comprised of eight shared latches. Only one side can control

the latch (semaphore) at any time. Control of a semaphore indicates

that a shared resource is in use. An automatic power-down feature is

controlled independently on each port by the chip enable pins.

The CY7C027/028 and CY7C037/038 are available in 100-pin

Thin Quad Plastic Flatpack (TQFP) packages.

Pin Configurations

100-Pin TQFP (Top View)

Note:

6. This pin is NC for CY7C027.

1

3

2

92 91 90 848587 868889 83 82 81 7678 77798093949596979899100

59

60

61

67

66

64

65

63

62

68

69

70

75

73

74

72

71

A9R

A10R

A11R

A12R

A13R

A14R

UB

R

NC

LBR

CE1R

SEMR

OER

GND

NC

A15R

GND

R/WR

GND

I/O15R

I/O14R

I/O13R

I/O12R

I/O11R

I/O10R

CE0R

58

57

56

55

54

53

52

51

CY7C027 (32K x 16)

A9L

A10L

A11L

A12L

A13L

A14L

UBL

NC

LBL

CE1L

SEML

OEL

GND

NC

A15L

VCC

R/WL

GND

I/O15L

I/O14L

I/O13L

I/O12L

I/O11L

I/O10L

CE0L

17

16

15

9

10

12

11

13

14

8

7

6

4

5

18

19

20

21

22

23

24

25

A8L

A7L

A6L

A5L

A4L

A3L

INTL

A1L

NC

GND

M/S

A0R

A1R

A0L

A2L

BUSYR

INTR

A2R

A3R

A4R

A5R

A6R

A7R

A8R

BUSYL

34 35 36 424139 403837 43 44 45 5048 494746

NC

I/O9R

I/O8R

I/O7R

VCC

I/O6R

I/01R

I/O4R

I/O2R

GND

I/O0L

I/O2L

I/O3L

I/O3R

I/O5R

I/O1L

GND

I/O4L

I/O5L

I/O6L

I/O7L

VCC

I/O8L

I/O9L

I/O0R

3332313029282726

CY7C028 (64K x 16)

[6]

CY7C027/028

CY7C037/038

Document #: 38-06042 Rev. *A Page 3 of 19

Pin Configurations (continued)

100-Pin TQFP (Top View)

Note:

7. This pin is NC for CY7C037.

Selection Guide

CY7C027/028

CY7C037/038

-12

[1]

CY7C027/028

CY7C037/038

-15

CY7C027/028

CY7C037/038

-20

Maximum Access Time (ns) 12 15 20

Typical Operating Current (mA) 195 190 180

Typical Standby Current for I

SB1

(mA) (Both ports TTL level) 55 50 45

Typical Standby Current for I

SB3

(mA) (Both ports CMOS level) 0.05 0.05 0.05

1

3

2

92 91 90 848587 868889 83 82 81 7678 77798093949596979899100

59

60

61

67

66

64

65

63

62

68

69

70

75

73

74

72

71

A8R

A9R

A10R

A11R

A12R

A13R

CE0

R

A15R

UBR

SEMR

R/WR

GND

I/O17R

LB

R

A14R

GND

OE

R

GND

I/O16R

I/O15R

I/O14R

I/O13R

I/O12R

I/O11R

CE1R

58

57

56

55

54

53

52

51

CY7C037 (32K x 18)

A9L

A10L

A11L

A12L

A13L

A14L

CE1L

LB

L

CE0L

R/WL

OEL

I/O17L

I/O16L

UB

L

A15L

VCC

GND

I/O15L

I/O14L

I/O13L

I/O12L

I/O11L

I/O10L

SEM

L

17

16

15

9

10

12

11

13

14

8

7

6

4

5

18

19

20

21

22

23

24

25

A8L

A7L

A6L

A5L

A4L

A3L

BUSYL

A1L

INTL

GND

VCC

INTR

A0R

A0L

A2L

M/S

BUSYR

A1R

A2R

A3R

A4R

A5R

A6R

A7R

GND

34 35 36 424139 403837 43 44 45 5048 494746

I/O10R

I/O9R

I/O8R

I/O7R

VCC

I/O6R

I/01R

I/O4R

I/O2R

GND

I/O0L

I/O2L

I/O3L

I/O3R

I/O5R

I/O1L

GND

I/O4L

I/O5L

I/O6L

I/O7L

VCC

I/O8L

I/O9L

I/O0R

3332313029282726

CY7C038 (64K x 18)

[7]

CY7C037-15AC

CY7C037-15AC

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