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74FCT163373APVG

P1-P3P4-P6P7-P7
1
IDT74FCT163373A/C
3.3V CMOS 16-BIT TRANSPARENT LATCH
INDUSTRIAL TEMPERATURE RANGE
SEPTEMBER 2009INDUSTRIAL TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
© 2009 Integrated Device Technology, Inc. DSC-5416/6
FEATURES:
• 0.5 MICRON CMOS Technology
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
•VCC = 3.3V ± 0.3V, Normal Range, or VCC = 2.7V to 3.6V, Extended
Range
• CMOS power levels (0.4
μ μ
μ μ
μ W typ. static)
• Rail-to-rail output swing for increased noise margin
• Low Ground Bounce (0.3V typ.)
• Inputs (except I/O) can be driven by 3.3V or 5V components
• Available in SSOP and TSSOP packages
FUNCTIONAL BLOCK DIAGRAM
IDT74FCT163373A/C
3.3V CMOS 16-BIT
TRANSPARENT LATCH
DESCRIPTION:
The FCT163373 16-bit transparent D-type latches are built using
advanced dual metal CMOS technology. These high-speed, low-power
latches are ideal for temporary storage of data. They can be used for
implementing memory address latches, I/O ports, and bus drivers. The
Output Enable and Latch Enable controls are organized to operate each
device as two 8-bit latches or one 16-bit latch. Flow-through organization
of signal pins simplifies layout. All inputs are designed with hysteresis for
improved noise margin.
The inputs of FCT163373 can be driven from either 3.3V or 5V devices.
This feature allows the use of these transparent latches as translators in a
mixed 3.3V/5V supply system. With xLE inputs high, the FCT163373 can
be used as a buffer to connect 5V components to a 3.3V bus.
2O1
2
OE
2LE
2D1
TO SEVEN OTHER CHANNELS
C
D
1OE
1LE
1O1
1
D1
TO SEVEN OTHER CHANNELS
C
D
1
48
47
2
24
25
36
13
2
INDUSTRIAL TEMPERATURE RANGE
IDT74FCT163373A/C
3.3V CMOS 16-BIT TRANSPARENT LATCH
Symbol Description Max Unit
VTERM
(2)
Terminal Voltage with Respect to GND –0.5 to +4.6 V
VTERM
(3)
Terminal Voltage with Respect to GND –0.5 to 7 V
VTERM
(4)
Terminal Voltage with Respect to GND –0.5 to VCC+0.5 V
TSTG Storage Temperature –65 to +150 ° C
I
OUT DC Output Current –60 to +60 mA
ABSOLUTE MAXIMUM RATINGS
(1)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. Vcc terminals.
3. Input terminals.
4. Outputs and I/O terminals.
Symbol Parameter
(1)
Conditions Typ. Max. Unit
CIN Input Capacitance VIN = 0V 3.5 6 pF
C
OUT Output Capacitance VOUT = 0V 3.5 8 pF
CAPACITANCE (TA = +25°C, F = 1.0MHz)
NOTE:
1. This parameter is measured at characterization but not tested.
PIN CONFIGURATION
SSOP/ TSSOP
TOP VIEW
Pin Names Description
x D x Data Inputs
xLE Latch Enable Input (Active HIGH)
xOE Output Enable Input (Active LOW)
xOx 3-State Outputs
PIN DESCRIPTION
FUNCTION TABLE
(1)
Inputs Outputs
xDx xLE xOE xBx
HHL H
LHL L
XLL O
(2)
XXH Z
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High-Impedance
2. Output level before the indicated steady-state input conditions were established.
1
O
1
GND
1
O
3
V
CC
1
OE
GND
2
O
2
GND
V
CC
GND
1
O
2
1
O
4
1
O
5
1
O
6
1
O
7
1
O
8
2
O
1
2
O
3
2
O
4
2
O
5
2
O
7
2
O
8
2
O
6
2
OE
1
LE
1
D
1
1
D
2
GND
1
D
3
1
D
4
V
CC
1
D
5
1
D
6
1
D
7
1
D
8
2
D
1
2
D
2
2
D
3
2
D
4
V
CC
2
D
5
2
D
7
2
D
8
2
D
6
2
LE
GND
GND
GND
39
29
30
31
32
33
34
35
36
37
38
25
26
27
28
48
47
41
42
43
44
45
46
40
1
2
3
4
5
6
7
8
9
10
12
13
14
15
16
17
18
19
20
11
21
22
23
24
3
IDT74FCT163373A/C
3.3V CMOS 16-BIT TRANSPARENT LATCH
INDUSTRIAL TEMPERATURE RANGE
Symbol Parameter Test Conditions
(1)
Min. Typ.
(2)
Max. Unit
VIH Input HIGH Level (Input pins) Guaranteed Logic HIGH Level 2 — 5.5 V
Input HIGH Level (I/O pins) 2 — VCC+0.5
VIL Input LOW Level (Input and I/O pins) Guaranteed Logic LOW Level –0.5 — 0.8 V
IIH Input HIGH Current (Input pins) VCC = Max. VI = 5.5V — — ±1
Input HIGH Current (I/O pins) V
I = VCC ——±1µA
I
IL Input LOW Current (Input pins) VI = GND — — ±1
Input LOW Current (I/O pins) VI = GND — — ±1
IOZH High Impedance Output Current VCC = Max. VO = VCC ——±1µA
IOZL (3-State Output pins) VO = GND — — ±1
VIK Clamp Diode Voltage VCC = Min., IIN = –18mA — –0.7 –1.2 V
IODH Output HIGH Current VCC = 3.3V, VIN = VIH or VIL, VO = 1.5V
(3)
–36 –60 –110 mA
IODL Output LOW Current VCC = 3.3V, VIN = VIH or VIL, VO = 1.5V
(3)
50 90 200 mA
V
OH Output HIGH Voltage VCC = Min. IOH = –0.1mA VCC-0.2 — —
V
IN = VIH or VIL IOH = –3mA 2.4 3 — V
VCC = 3V IOH = –8mA 2.4
(5)
3—
VIN = VIH or VIL
VOL Output LOW Voltage VCC = Min. IOL = 0.1mA — — 0.2
VIN = VIH or VIL IOL = 16mA — 0.2 0.4
I
OL = 24mA — 0.3 0.55 V
VCC = 3V IOL = 24mA — 0.3 0.5
VIN = VIH or VIL
IOS Short Circuit Current
(4)
VCC = Max., VO = GND
(3)
–60 –135 –240 mA
VH Input Hysteresis — — 150 — mV
I
CCL Quiescent Power Supply Current VCC = Max. — 0.1 10 µA
ICCH VIN = GND or VCC
ICCZ
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: TA = –40°C to +85°C, VCC = 2.7V to 3.6V
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 3.3V, +25°C ambient.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
4. This parameter is guaranteed but not tested.
5. VOH = VCC–0.6V at rated current.
P1-P3P4-P6P7-P7

74FCT163373APVG

Mfr. #:
Buy 74FCT163373APVG
Manufacturer:
IDT
Description:
Latches 16BIT BUFF/DRIVER
Lifecycle:
New from this manufacturer.
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