Summary description M27C2001
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Figure 4. TSOP Connections
A1
A0
Q0
A7
A4 A3
A2
A6
A5
A13
A10
A8
A9
Q7
A14
A11 G
E
Q5
Q1
Q2
Q3
Q4
Q6
A17
P
A16
A12
V
PP
V
CC
A15
AI01153B
M27C2001
(Normal)
8
1
9
16 17
24
25
32
V
SS
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M27C2001 Device operation
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2 Device operation
The operating modes of the M27C2001 are listed in the Table 2. A single power supply is
required in the read mode. All inputs are TTL levels except for V
PP
and 12V on A9 for
Electronic Signature.
2.1 Read Mode
The M27C2001 has two control functions, both of which must be logically active in order to
obtain data at the outputs. Chip Enable (E
) is the power control and should be used for
device selection. Output Enable (G
) is the output control and should be used to gate data to
the output pins, independent of device selection. Assuming that the addresses are stable,
the address access time (t
AVQV
) is equal to the delay from E to output (t
ELQV
). Data is
available at the output after a delay of t
GLQV
from the falling edge of G, assuming that E has
been low and the addresses have been stable for at least t
AVQV
-t
GLQV
.
2.2 Standby Mode
The M27C2001 has a standby mode which reduces the supply current from 30mA to 100µA.
The M27C2001 is placed in the standby mode by applying a CMOS high signal to the E
input. When in the standby mode, the outputs are in a high impedance state, independent of
the G
input.
2.3 Two Line Output Control
Because EPROM devices are usually used in larger memory arrays, this product features a
2 line control function which accommodates the use of multiple memory connection. The
two line control function allows:
a) the lowest possible memory power dissipation,
b) complete assurance that output bus contention will not occur.
For the most efficient use of these two control lines, E
should be decoded and used as the
primary device selecting function, while G
should be made a common connection to all
devices in the array and connected to the READ
line from the system control bus. This
ensures that all deselected memory devices are in their low power standby mode and that
the output pins are only active when data is required from a particular memory device.
2.4 System Considerations
The power switching characteristics of Advanced CMOS EPROMs require careful
decoupling of the devices. The supply current, I
CC
, has three segments that are of interest to
the system designer: the standby current level, the active current level, and transient current
peaks that are produced by the falling and rising edges of E
. The magnitude of the transient
current peaks is dependent on the capacitive and inductive loading of the device at the
output. The associated transient voltage peaks can be suppressed by complying with the
two line output control and by properly selected decoupling capacitors. It is recommended
that a 0.1µF ceramic capacitor be used on every device between V
CC
and V
SS
. This should
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Device operation M27C2001
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be a high frequency capacitor of low inherent inductance and should be placed as close to
the device as possible. In addition, a 4.7µF bulk electrolytic capacitor should be used
between V
CC
and V
SS
for every eight devices. The bulk capacitor should be located near the
power supply connection point. The purpose of the bulk capacitor is to overcome the voltage
drop caused by the inductive effects of PCB traces.
2.5 Programming
When delivered (and after each erasure for UV EPROM), all bits of the M27C2001 are in the
'1' state. Data is introduced by selectively programming '0's into the desired bit locations.
Although only '0's will be programmed, both '1's and '0's can be present in the data word.
The only way to change a '0' to a '1' is by die exposure to ultraviolet light (UV EPROM). The
M27C2001 is in the programming mode when V
PP
input is at 12.75V, E is at V
IL
and P is
pulsed to V
IL
. The data to be programmed is applied to 8 bits in parallel to the data output
pins. The levels required for the address and data inputs are TTL. V
CC
is specified to be
6.25 ± 0.25V.
2.6 PRESTO II Programming Algorithm
PRESTO II Programming Algorithm allows the whole array to be programmed with a
guaranteed margin, in a typical time of 26.5 seconds. Programming with PRESTO II
consists of applying a sequence of 100µs program pulses to each byte until a correct verify
occurs (see Figure 5). During programming and verify operation, a MARGIN MODE circuit is
automatically activated in order to guarantee that each cell is programmed with enough
margin. No overprogram pulse is applied since the verify in MARGIN MODE provides the
necessary margin to each programmed cell.
Figure 5. Programming Flowchart
AI00715C
n = 0
Last
Addr
VERIFY
P = 100µs Pulse
++n
= 25
++ Addr
V
CC
= 6.25V, V
PP
= 12.75V
FAIL
CHECK ALL BYTES
1st: V
CC
= 6V
2nd: V
CC
= 4.2V
YES
NO
YES
NO
YES
NO
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M27C2001-12F6

Mfr. #:
Manufacturer:
STMicroelectronics
Description:
EPROM 2M (256Kx8) 120ns
Lifecycle:
New from this manufacturer.
Delivery:
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