AD2S1200
Rev. 0 | Page 15 of 24
t
11
t
SCLK
t
10
t
9
t
8
04406-0-008
SCLK
SO
MSB MSB–1 LSB RDVEL DOS LOT PAR
RD
t
3
t
6
t
7
t
CK
CLKIN
SO
VELPOS
t
2
SAMPLE
CS
RD
RDVEL
t
1
t
1
t
3
t
5
t
4
t
5
t
4
t
7
t
6
Figure 8. Serial Port Read Timing
Table 6. Serial Port Timing
Parameter Description Min Typ Max
t
8
MSB Read Time from RD
/CS to SCLK
15 ns t
SCLK
t
9
Enable Time RD
/CS to DB Valid
12 ns
t
10
Delay SCLK to DB Valid 14 ns
t
11
Disable Time RD
/CS to DB High Z
18 ns
t
SCLK
Serial Clock Period (25 MHz Max) 40 ns
AD2S1200
Rev. 0 | Page 16 of 24
INCREMENTAL ENCODER OUTPUTS
The incremental encoder emulation outputs A, B, and NM are
free running and are always valid, providing that valid resolver
format input signals are applied to the converter.
The AD2S1200 emulates a 1024-line encoder. Relating this to
converter resolution means one revolution produces 1,024 A, B
pulses. A leads B for increasing angular rotation (i.e., clockwise
direction). The addition of the DIR output negates the need for
external A and B direction decode logic. The DIR output
indicates the direction of the input rotation and it is high for
increasing angular rotation. DIR can be considered as an
asynchronous output and can make multiple changes in state
between two consecutive LSB update cycles. This occurs when
the direction of rotation of the input changes but the magnitude
of the rotation is less than 1 LSB.
The north marker pulse is generated as the absolute angular
position passes through zero. The north marker pulse width is
set internally for 90° and is defined relative to the A cycle.
Figure 9 details the relationship between A, B, and NM.
04406-0-009
A
B
NM
Figure 9. A, B, and NM Timing for Clockwise Rotation
Unlike incremental encoders, the AD2S1200 encoder output is
not subject to error specifications such as cycle error, eccentric-
ity, pulse and state width errors, count density, and phase ϕ. The
maximum speed rating,
n, of an encoder is calculated from its
maximum switching frequency,
f
MAX
, and its pulses per revo-
lution (
PPR).
PPR
f
n
MAX
×
=
60
The AD2S1200 A, B pulses are initiated from XTALOUT, which
has a frequency of 4.096 MHz. The equivalent encoder
switching frequency is
)14(024.1096.44/1 PulseUpdatesMHzMHz ==×
At 12 bits, the PPR = 1,024. Therefore, the maximum speed, n,
of the AD2S1200 is
rpmn 60000
024,1
000,024,160
=
×
=
To get a maximum speed of 60,000 rpm, an external crystal of
8.192 MHz has to be chosen in order to produce an internal
CLOCKOUT equal to 4.096 MHz.
This compares favorably with encoder specifications where f
MAX
is specified from 20 kHz (photo diodes) to 125 kHz (laser
based) depending on the light system used. A 1,024 line laser-
based encoder will have a maximum speed of 7,300 rpm.
The inclusion of A, B outputs allows the AD2S1200 plus
resolver solution to replace optical encoders directly without the
need to change or upgrade existing application software.
ON-BOARD PROGRAMMABLE SINUSOIDAL
OSCILLATOR
An on-board oscillator provides the sinusoidal excitation signal
(EXC) to the resolver as well as its complemented signal (
EXC
).
The frequency of this reference signal is programmable to four
standard frequencies (10 kHz, 12 kHz, 15 kHz, or 20 kHz) using
the FS1 and FS2 pins (see Table 7). FS1 and FS2 have internal pull-
ups, so the default frequency is 10 kHz. The amplitude of this
signal is centered on 2.5 V and has an amplitude of 3.6 V p-p.
Table 7. Excitation Frequency Selection
Frequency Selection (kHz) FS1 FS2
10 1 1
12 1 0
15 0 1
20 0 0
The reference output of the AD2S1200 will need an external
buffer amplifier to provide gain and the additional current to
drive a resolver. Refer to Figure 6 for a suggested buffer circuit.
The AD2S1200 also provides an internal synchronous reference
signal that is phase locked to its Sin and Cos inputs. Phase
errors between the resolver primary and secondary windings
could degrade the accuracy of the RDC and are compensated by
this synchronous reference signal. This also compensates the
phase shifts due to temperature and cabling and eliminates the
need of an external preset phase compensation circuits.
AD2S1200
Rev. 0 | Page 17 of 24
Synthetic Reference Generation
When a resolver undergoes a high rotation rate, the RDC tends
to act as an electric motor and produces speed voltages, along
with the ideal Sin and Cos outputs. These speed voltages are in
quadrature to the main signal waveform. Moreover, nonzero
resistance in the resolver windings causes a non-zero phase shift
between the reference input and the Sin and Cos outputs. The
combination of speed voltages and phase shift causes a tracking
error in the RDC that is approximated by
FrequencyReference
RateRotation
ShiftPhaseError
×=
To compensate for the described phase error between the
resolver reference excitation and the Sin/Cos signals, an internal
synthetic reference signal is generated in phase with the refer-
ence frequency carrier. The synthetic reference is derived using
the internally filtered Sin and Cos signals. It is generated by
determining the zero crossing of either the Sin or Cos (which-
ever signal is larger, to improve phase accuracy) and evaluating
the phase of the resolver reference excitation. The synthetic
reference reduces the phase shift between the reference and
Sin/Cos inputs to less than 10°, and will operate for phase shifts
of ±45°.
SUPPLY SEQUENCING AND RESET
The AD2S1200 requires an external reset signal to hold the
RESET
input low until V
DD
is within the specified operating
range of 4.5 V to 5.5 V.
The
RESET
pin must be held low for a minimum of 10 µs after
V
DD
is within the specified range (t
RST
in Figure 10). Applying a
RESET
signal to the AD2S1200 initializes the output position to
a value of 0x000 (degrees output through the parallel, serial, and
encoder interfaces) and causes LOS to be indicated (LOT and
DOS pins pulled low) as shown in Figure 10.
Failure to apply the above (correct) power-up/reset sequence
can result in an incorrect position indication.
After a rising edge on the
RESET
input, the device must be
allowed at least 20 ms (t
TRACK
) as shown in Figure 10 for internal
circuitry to stabilize and the tracking loop to settle to the step
change in input position. After t
TRACK
, a
SAMPLE
pulse must be
applied, releasing the LOT and DOT pins to the state deter-
mined by the fault detection circuitry and providing valid
position data at the parallel and serial outputs (note that if
position data is being acquired via the encoder outputs, they
may be monitored during t
TRACK
).
The
RESET
pin is internally pulled up.
t
RST
t
RST
04406-0-010
V
DD
RESET
4.75V
VALID
OUTPUT
DATA
SAMPLE
LOT
DOS
t
TRACK
Figure 10. Power Supply Sequencing and Reset
CHARGE PUMP OUTPUT
A 204.8 kHz square wave output with 50% duty cycle is avail-
able at the CPO output pin of the AD2S1200. This square wave
output can be used for negative rail voltage generation, or to
create a V
CC
rail.

AD2S1200YSTZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Data Acquisition ADCs/DACs - Specialized IC12-Bit R/D Cnvtr w/Ref Oscillator
Lifecycle:
New from this manufacturer.
Delivery:
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