1/14November 2004
HIGH SPEED:
f
MAX
= 270 MHz (TYP.) at V
CC
= 5V
LOW POWER DISSIPATION:
I
CC
= 4 µA (MAX.) at T
A
=25°C
HIGH NOISE IMMUNITY:
V
NIH
= V
NIL
= 28% V
CC
(MIN.)
POWER DOWN PROTECTION ON INPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 8 mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 5.5V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 374
IMPROVED LATCH-UP IMMUNITY
LOW NOISE: V
OLP
= 0.9V (MAX.)
DESCRIPTION
The 74VHC374 is an advanced high-speed
CMOS OCTAL D-TYPE FLIP FLOP with 3 STATE
OUTPUTS NON INVERTING fabricated with
sub-micron silicon gate and double-layer metal
wiring C
2
MOS technology.
These 8 bit D-Type latch are controlled by a clock
input (CK) and an output enable input (OE
).
On the positive transition of the clock, the Q
outputs will be set to the logic state that were
setup at the D inputs.
While the (OE
) input is low, the 8 outputs will be in
a normal logic state (high or low logic level) and
while high level the outputs will be in a high
impedance state.
The Output control does not affect the internal
operation of flip flops; that is, the old data can be
retained or the new data can be entered even
while the outputs are off. Power down protection is
provided on all inputs and 0 to 7V can be accepted
on inputs with no regard to the supply voltage.
This device can be used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74VHC374
OCTAL D-TYPE FLIP FLOP
WITH 3 STATE OUTPUTS NON INVERTING
Figure 1: Pin Connection And IEC Logic Symbols
Table 1: Order Codes
PACKAGE T & R
SOP 74VHC374MTR
TSSOP 74VHC374TTR
TSSOPSOP
Rev. 4
Obsolete Product(s) - Obsolete Product(s)
74VHC374
2/14
Figure 2: Input Equivalent Circuit Table 2: Pin Description
Table 3: Truth Table
X : Don’t Care
Z : High Impedance
Figure 3: Logic Diagram
This logic diagram has not be used to estimate propagation delays
PIN N° SYMBOL NAME AND FUNCTION
1OE
3 State Output Enable
Input (Active LOW)
2, 5, 6, 9, 12,
15, 16,19
Q0 to Q7 3-State Outputs
3, 4, 7, 8, 13,
14, 17, 18
D0 to D7 Data Inputs
11 CK Clock
10 GND Ground (0V)
20 V
CC
Positive Supply Voltage
INPUTS OUTPUT
OE
CK D Q
HXXZ
L X NO CHANGE
LLL
LHH
Obsolete Product(s) - Obsolete Product(s)
74VHC374
3/14
Table 4: Absolute Maximum Ratings
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
Table 5: Recommended Operating Conditions
1) V
IN
from 30% to 70% of V
CC
Symbol Parameter Value Unit
V
CC
Supply Voltage
-0.5 to +7.0 V
V
I
DC Input Voltage
-0.5 to +7.0 V
V
O
DC Output Voltage -0.5 to V
CC
+ 0.5
V
I
IK
DC Input Diode Current
- 20 mA
I
OK
DC Output Diode Current
± 20 mA
I
O
DC Output Current
± 25 mA
I
CC
or I
GND
DC V
CC
or Ground Current
± 75 mA
T
stg
Storage Temperature
-65 to +150 °C
T
L
Lead Temperature (10 sec)
300 °C
Symbol Parameter Value Unit
V
CC
Supply Voltage
2 to 5.5 V
V
I
Input Voltage
0 to 5.5 V
V
O
Output Voltage 0 to V
CC
V
T
op
Operating Temperature
-55 to 125 °C
dt/dv
Input Rise and Fall Time (note 1) (V
CC
= 3.3 ± 0.3V)
(V
CC
= 5.0 ± 0.5V)
0 to 100
0 to 20
ns/V
Obsolete Product(s) - Obsolete Product(s)

74VHC374MTR

Mfr. #:
Manufacturer:
STMicroelectronics
Description:
Flip Flops Quad "D" Latch
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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