MC74LVX8053
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10
R
L
Figure 12. Crosstalk Between Any Two
Switches, Test Set−Up
Figure 13. Power Dissipation Capacitance,
Test Set−Up
Figure 14a. Total Harmonic Distortion, Test Set−Up Figure 14b. Plot, Harmonic Distortion
0
−10
−20
−30
−40
−50
100
1.0 2.0 3.125
FREQUENCY (kHz)
dB
−60
−70
−80
−90
FUNDAMENTAL FREQUENCY
DEVICE
SOURCE
ON
6
8
16
C
L
*
*Includes all probe and jig capacitance
OFF
R
L
R
L
V
IS
R
L
C
L
*
V
OS
f
in
0.1F
ON/OFF
6
8
16
V
CC
CHANNEL SELECT
NC
COMMON O/I
OFF/ON
ANALOG I/O
V
CC
A
11
V
CC
ON
6
8
16
V
CC
0.1F
C
L
*
f
in
R
L
TO
DISTORTION
METER
*Includes all probe and jig capacitance
V
OS
V
IS
APPLICATIONS INFORMATION
The Channel Select and Enable control pins should be at
V
CC
or GND logic levels. V
CC
being recognized as a logic
high and GND being recognized as a logic low. In this
example:
V
CC
= +5V = logic high
GND = 0V = logic low
The maximum analog voltage swing is determined by the
supply voltages V
CC
. The positive peak analog voltage
should not exceed V
CC
. Similarly, the negative peak analog
voltage should not go below GND. In this example, the
difference between V
CC
and GND is five volts. Therefore,
using the configuration of Figure 15, a maximum analog
signal of five volts peak−to−peak can be controlled. Unused
analog inputs/outputs may be left floating (i.e., not
connected). However, tying unused analog inputs and
outputs to V
CC
or GND through a low value resistor helps
minimize crosstalk and feedthrough noise that may be
picked up by an unused switch.
Although used here, balanced supplies are not a
requirement. The only constraints on the power supplies are
that:
V
CC
− GND = 2 to 6 volts
When voltage transients above V
CC
and/or below GND
are anticipated on the analog channels, external Germanium
or Schottky diodes (D
x
) are recommended as shown in
Figure 16. These diodes should be able to absorb the
maximum anticipated current surges during clipping.
MC74LVX8053
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11
ANALOG
SIGNAL
Figure 15. Application Example Figure 16. External Germanium or
Schottky Clipping Diodes
a. Using Pull−Up Resistors b. Using HCT Interface
Figure 17. Interfacing LSTTL/NMOS to CMOS Inputs
ON
6
8
16
+5V
ANALOG
SIGNAL
+5V
0V
+5V
0V
11
10
9
TO EXTERNAL CMOS
CIRCUITRY 0 to 5V
DIGITAL SIGNALS
ON/OFF
8
16
V
CC
V
EE
D
x
V
CC
D
x
V
EE
D
x
V
CC
D
x
ANALOG
SIGNAL
ON/OFF
6
8
16
+5V
ANALOG
SIGNAL
+5V
GND
+5V
GND
11
10
9
R
*
R R
LSTTL/NMOS
CIRCUITRY
+5V
* 2K R 10K
ANALOG
SIGNAL
ON/OFF
6
8
16
+5V
ANALOG
SIGNAL
+5V
GND
+5V
GND
11
10
9
LSTTL/NMOS
CIRCUITRY
+5V
VHC1GT50
BUFFERS
Figure 18. Function Diagram, LVX8053
13
X1
12
X0
1
Y1
2
Y0
3
Z1
5
Z0
14
X
LEVEL
SHIFTER
LEVEL
SHIFTER
LEVEL
SHIFTER
LEVEL
SHIFTER
11
A
10
B
9
C
6
ENABLE
15
Y
4
Z
MC74LVX8053
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12
PACKAGE DIMENSIONS
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
18
16 9
SEATING
PLANE
F
J
M
R
X 45
G
8 PLP
−B−
−A−
M
0.25 (0.010) B
S
−T−
D
K
C
16 PL
S
B
M
0.25 (0.010) A
S
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A 9.80 10.00 0.386 0.393
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
G 1.27 BSC 0.050 BSC
J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0 7 0 7
P 5.80 6.20 0.229 0.244
R 0.25 0.50 0.010 0.019

SOIC−16
D SUFFIX
CASE 751B−05
ISSUE J
TSSOP−16
DT SUFFIX
CASE 948F−01
ISSUE A
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A 4.90 5.10 0.193 0.200
B 4.30 4.50 0.169 0.177
C −−− 1.20 −−− 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
G 0.65 BSC 0.026 BSC
H 0.18 0.28 0.007 0.011
J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K 0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L 6.40 BSC 0.252 BSC
M 0 8 0 8
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.

SECTION N−N
SEATING
PLANE
IDENT.
PIN 1
1
8
16
9
DETAIL E
J
J1
B
C
D
A
K
K1
H
G
DETAIL E
F
M
L
2X L/2
−U−
S
U0.15 (0.006) T
S
U0.15 (0.006) T
S
U
M
0.10 (0.004) V
S
T
0.10 (0.004)
−T−
−V−
−W−
0.25 (0.010)
16X REFK
N
N

MC74LVX8053DR2

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Multiplexer Switch ICs 2-6V ANLG Mux/Demux
Lifecycle:
New from this manufacturer.
Delivery:
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