I
NTEGRATED
C
IRCUITS
D
IVISION
CPC7592
R04 www.ixysic.com 15
Forcing T
SD
to a logic high disables the thermal
shutdown circuit and is therefore not recommended as
this could lead to device damage or destruction in the
presence of excessive tip or ring potentials.
Break-Before-Make Ringing to Talk Transition Logic Sequence for all Versions
2.4 Data Latch
The CPC7592 has an integrated transparent data
latch. The latch enable operation is controlled by TTL
logic input levels at the LATCH pin. Data input to the
latch is via the input pins IN
RINGING
and IN
TEST
while
the output of the data latch are internal nodes used for
state control. When the LATCH enable control pin is at
a logic 0 the data latch is transparent and the input
control signals flow directly through the data latch to
the state control circuitry. A change in input will be
reflected by a change in the switch state.
Whenever the LATCH enable control pin is at logic 1,
the data latch is active and data is locked. Subsequent
changes to the input controls IN
RINGING
and IN
TEST
will not result in a change to the control logic or affect
the existing switch state.
The switches will remain in the state they were in
when the LATCH changes from logic 0 to logic 1 and
will not respond to changes in input as long as the
LATCH is at logic 1. However, neither the T
SD
input
nor the T
SD
output control functions are affected by
the latch function. Since internal thermal shutdown
control and external “All-off” control is not affected by
the state of the LATCH enable input, T
SD
will override
state control.
2.5 T
SD
Pin Description
The T
SD
pin is a bi-directional I/O structure with an
internal pull-up current source with a nominal value of
16 A biased from V
DD
. As an output, this pin
indicates the status of the thermal shutdown circuitry.
Typically, during normal operation, this pin will be
pulled up to V
DD
but under fault conditions that create
excess thermal loading the CPC7592 will enter
thermal shutdown and a logic low will be output.
As an input, the T
SD
pin is utilized to place the
CPC7592 into the “All-Off” state by simply pulling the
input low. For applications using low-voltage logic
devices (lower than V
DD
), IXYS IC Division
recommends the use of an open-collector or an
open-drain type output to control T
SD
. This avoids
sinking the T
SD
pull up bias current to ground during
normal operation when the all-off state is not required.
In general, IXYS IC Division recommends all
applications use an open-collector or open-drain type
device to drive this pin.
Setting T
SD
to a logic 1 or tying this pin to V
CC
allows
switch control using the logic inputs. This setting,
however, also disables the thermal shutdown circuit
and is therefore not recommended. As a result the
T
SD
pin has two recommended operating states when
it is used as an input control. A logic 0, which forces
State
IN
RINGING
IN
TEST
LATCH
T
SD
Timing
Break
Switches
Ringing
Return
Switch
(SW3)
Ringing
Switch
(SW4)
Test
Switches
Ringing 1 0 0 Z - Off
On On Off
All-Off 1 0
X0
Hold this state for at least one-half of the
ringing cycle. SW4 waiting for zero current to
turn off.
Off Off
On Off
Break-
Before-
Make
0 0 SW4 has opened Off Off Off Off
Talk 0 0 0 Z Close Break Switches
On Off Off Off
