4
Typical Application/Operation
Introduction to Fault Detection and Protection
The power stage of a typical three phase inverter is susceptible to several types of failures, most of which are potentially
destructive to the power IGBTs. These failure modes can be grouped into four basic categories: phase and/or rail supply
short circuits due to user misconnect or bad wiring, control signal failures due to noise or computational errors, overload
conditions induced by the load, and component failures in the gate drive circuitry. Under any of these fault conditions,
the current through the IGBTs can increase rapidly, causing excessive power dissipation and heating. The IGBTs become
damaged when the current load approaches the saturation current of the device, and the collector to emitter voltage
rises above the saturation voltage level. The drastically increased power dissipation very quickly overheats the power
device and destroys it. To prevent damage to the drive, fault protection must be implemented to reduce or turn-o the
overcurrent during a fault condition.
A circuit providing fast local fault detection and shutdown is an ideal solution, but the number of required components,
board space consumed, cost, and complexity have until now limited its use to high performance drives. The features
which this circuit must have are high speed, low cost, low resolution, low power dissipation, and small size.
The ACPL-34JT satises these criteria by combining a high speed, high output current driver, high voltage optical isola-
tion between the input and output, local IGBT desaturation detection and shut down, and optically isolated fault and
UVLO status feedback signal into a single 16-pin surface mount package.
The fault detection method, which is adopted in the ACPL-34JT, is to monitor the saturation (collector) voltage of the
IGBT and to trigger a local fault shutdown sequence if the collector voltage exceeds a predetermined threshold. A small
gate discharge device slowly reduces the high short circuit IGBT current to prevent damaging voltage spikes. Before
the dissipated energy can reach destructive levels, the IGBT is shut o. During the o state of the IGBT, the fault detect
circuitry is simply disabled to prevent false ‘fault signals.
The alternative protection scheme of measuring IGBT current to prevent desaturation is eective if the short circuit
capability of the power device is known, but this method will fail if the gate drive voltage decreases enough to only
partially turn on the IGBT. By directly measuring the collector voltage, the ACPL-34JT limits the power dissipation in the
IGBT even with insucient gate drive voltage. Another more subtle advantage of the desaturation detection method
is that power dissipation in the IGBT is monitored, while the current sense method relies on a preset current threshold
to predict the safe limit of operation. Therefore, an overly- conservative overcurrent threshold is not needed to protect
the IGBT.
Recommended Application Circuit
The ACPL-34JT has non-inverting gate control inputs, and an open collector fault and UVLO outputs suitable for wired
‘OR’ applications.
The recommended application circuit shown in Figure 3 illustrates a typical gate drive implementation using the ACPL-
34JT.
The two supply bypass capacitors (0.1 μF) provide the large transient currents necessary during a switching transition.
The desat diode and 220pF blanking capacitor are the necessary external components for the fault detection circuitry.
The gate resistor (10Ω) serves to limit gate charge current and indirectly control the IGBT collector voltage rise and fall
times. The open collector fault and UVLO outputs have a passive 10kΩ pull-up resistor and a 330 pF ltering capacitor.
5
Description of Gate Driver and Miller Clamping
The gate driver is directly controlled by the LED current. When LED current is driven high, the output of ACPL-34JT can
deliver 2.5 A sourcing current to drive the IGBT’s gate. While LED is switched o, the gate driver can provide 2.5 A sink-
ing current to switch the gate o fast. Additional Miller clamping pull-down transistor is activated when output voltage
reaches about 2 V with respect to V
EE2
to provide low impedance path to Miller current as shown in Figure 5.
Figure 4. Gate Drive Signal Behavior
Figure 3. Typical gate drive circuit with Desat current sensing using ACPL-34JT
uC
+ 5V
LED2+
VCC2
VEE2
VO
VE
VEE1
VEE1
AN
CA
FAULT
UVLO
DESAT
VCC1
VEE1
SSD/CLAMP
10kΩ
10kΩ
10Ω
330pF
330pF
0.1uF
150Ω
1kΩ
220pF
ACPL-34JT
0.1uF
VEE2
VEE2
10uF
10uF
150Ω
VCC1
VCC2
DESAT Fault Detection Blanking Time
The DESAT fault detection circuitry must remain disabled for a short time period following the turn-on of the IGBT to
allow the collector voltage to fall below the DESAT theshold. This time period, called the DESAT blanking time, is con-
trolled by the internal DESAT charge current, the DESAT voltage threshold, and the external DESAT capacitor.
The nominal blanking time is calculated in terms of external capacitance (C
BLANK
), FAULT threshold voltage (V
DESAT
), and
DESAT charge current (I
CHG
) in addition to an internal DESAT blanking time (t
DESAT(BLANKING)
).
t
BLANK
= C
BLANK
x (V
DESAT
/I
CHG
) +
t
DESAT(BLANKING)
I
F
V
O
V
GATE
6
Description of Operation during Over Current Condition
1. DESAT terminal monitors IGBTs V
CE
voltage.
2. When the voltage on the DESAT terminal exceeds 7 volts, the output voltage (V
OUT
) to IGBT gate goes to Hi-Z state
and the SSD/CLAMP output is slowly lowered.
3. FAULT output goes low, notifying the microcontroller of the fault condition.
4. Microcontroller takes appropriate action.
5. When t
DESAT(MUTE)
expires LED input need to be kept low for t
DESAT(RESET)
before fault condition is cleared. FAULT
status will return to high and SSD/CLAMP output will return to Hi-Z state.
6. Output (V
OUT
) starts to respond to LED input after fault condition is cleared.
Description of UnderVoltage LockOut
Insucient gate voltage to IGBT can increase turn on resistance of IGBT, resulting in large power loss and IGBT damage
due to high heat dissipation. ACPL-34JT monitors the output power supply constantly. When output power supply is
lower than undervoltage lockout (UVLO) threshold gate driver output will shut o to protect IGBT from low voltage bias.
During power up, the UVLO feature forces the gate driver output to low to prevent unwanted turn-on at lower voltage.
Figure 5. Circuit Behaviors at Power up and Power down
Figure 6. Circuit Behaviors During Overcurrent Event
V
CC1
V
CC2
LED I
F
V
O
FAULT
UVLO
t
UVLO_ON
t
UVLO_OFF
t
PHL_UVLO
t
PLH_UVLO
V
UVLO+
V
UVLO -
t
DESAT(RESET)
t
DESAT(BLANKING)
I
F
V
DESAT
V
FAULT
V
O
state
Clamp State
Hi-Z
Hi-Z
V
GATE
Hi-Z
Clamp
Clamp
t
DESAT(MUTE)
Clamp
V
DESAT_TH
t
DESAT(90%)
t
DESAT(FAULT)

ACPL-34JT-500E

Mfr. #:
Manufacturer:
Broadcom / Avago
Description:
High Speed Optocouplers Optocouplers
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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