Document Number: 73868
S11-0975–Rev. C, 16-May-11
www.vishay.com
13
Vishay Siliconix
SiP11203, SiP11204
This document is subject to change without notice.
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The Figure 8 below shows how the rising edge delay is
implemented in conjunction with the Si9122 and allows
the effective BBM2 and BBM4 falling delays to be
modified independently of rising delays BBM1 and
BBM3. For definition of the BBM delays please see the
Si9122 datasheet
.
OUTPUT OVER-VOLTAGE PROTECTION
The SiP11203/SiP11204 provide output over-voltage
protection (OVP) by means of a dedicated internal
comparator. One input of the OVP comparator is
brought out to the OVP
IN
pin, and the other is returned
to an internal reference voltage that is fixed at 120 %
of the 1.225 V V
REF
value, or 1.47 V. A voltage in
excess of 1.47 V at the OVP
IN
pin indicates an OVP
fault.
The OVP circuitry operates in two different ways,
depending upon whether the SiP11203/SiP11204 is in
start-up mode, or in normal operation. In this context,
start-up mode is defined as device operation during
that period for which V
REF
is less than 90 % of its 1.225 V
value, or 1.1 V
.
Start-Up Mode:
If the 1.47 V OVP threshold is exceeded during start-
up, the driver outputs OUTA and OUTB are held low
until the voltage on the V
REF
pin has exceeded 1.1 V.
The driver outputs are then released to respond to INA
and INB.
Normal Operation Mode:
If the OVP threshold is exceeded, or remains
exceeded, after V
REF
has reached 1.1 V, the OVP latch
will be set. This will cause the driver outputs to be
forced high for SiP11203, or forced low for SiP11204.
At the same time, an on-chip transistor will discharge
the bypass capacitor at the V
REF
pin towards ground.
The OVP latch is reset when the logical and of two
conditions:
•
The voltage on the V
REF
pin must be
≤
20 % (245 mV)
of its nominal 1.225 V level, to ensure an orderly
soft-start cycle when operation resumes, and
• The voltage at the OVP
IN
pin must be 1.1 V,
indicating that the OVP fault has been cleared.
When the OVP latch is reset, the SiP11203/SiP11204
will release their outputs, and return to normal
operation via a soft-start cycle.
To prevent spurious activation of the over-voltage
function, the over-voltage condition must be present for
five switching instances, where a switching instance is
defined as activity on either IN
A
or IN
B
. On the fifth
switching instance the overvoltage condition is latched.
If the over voltage condition disappears the IC will not
recognize an over-voltage as being present and the
counter will be reset to zero.
Note that the OVP
IN
threshold voltage is derived from
the internal 2.5 V reference voltage V
REFINT
, which is
derived from V
IN
, and therefore is not delayed by the
rise time of either V
L
or V
REF
.
Figure 8. The delay of SiP11203 and SiP11204 gate-drive output signals compensate the break-before-make switching action
discrepancies arising from propagation delays
PWM PWM
PWM
PWM
DL
DL
OUT A
OUT A
BBM1
BBM2
BBM3
BBM4
Rising edge
delay set by R
DEL
