PCA9513A_PCA9514A_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 18 August 2009 16 of 26
NXP Semiconductors
PCA9513A; PCA9514A
Hot swappable I
2
C-bus and SMBus bus buffer
[3] Delays that can occur after ENABLE and/or idle times have passed.
[4] Guaranteed by design, not production tested.
[5] I
trt(pu)
varies with temperature and V
CC
voltage, as shown in Section 11.1 “Typical performance characteristics”.
[6] Input pull-up voltage should not exceed power supply voltage in operating mode because the rise time accelerator will clamp the voltage
to the positive supply rail.
[7] The connection circuitry always regulates its output to a higher voltage than its input. The magnitude of this offset voltage as a function
of the pull-up resistor and V
CC
voltage is shown in Section 11.1 “Typical performance characteristics”.
[8] C
b
= total capacitance of one bus line in pF.
[9] Force V
SDAIN
=V
SCLIN
= 0.1 V, tie SDAOUT and SCLOUT through 10 k resistor to V
CC
and measure the SDAOUT and SCLOUT
output.
11.1 Typical performance characteristics
Fig 14. I
CC
versus temperature Fig 15. I
trt(pu)
versus temperature
C
i
=C
o
> 100 pF; R
PU(in)
=R
PU(out)
=10k
Fig 16. Input/output t
PHL
versus temperature Fig 17. Connection circuitry V
O
V
I
T
amb
(°C)
40 +90+25
002aab588
2.9
3.3
3.7
I
CC
(mA)
2.5
3.3 V
V
CC
= 5.5 V
2.7 V
T
amb
(°C)
40 +90+25
002aab590
4
8
12
I
trt(pu)
(mA)
0
3.0 V
V
CC
= 5 V
2.7 V
T
amb
(°C)
40 +90+25
002aab589
70
80
90
t
PHL
(ns)
60
3.3 V
V
CC
= 5.5 V
2.7 V
R
PU
(k)
0403010 20
002aab591
150
250
350
V
O
V
I
(mV)
50
V
CC
= 5 V
3.3 V
PCA9513A_PCA9514A_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 18 August 2009 17 of 26
NXP Semiconductors
PCA9513A; PCA9514A
Hot swappable I
2
C-bus and SMBus bus buffer
11.2 Timing diagrams
Fig 18. Timing for t
en
, t
idle(READY)
, and t
dis
002aab592
t
en
SDAn/SCLn
ENABLE
READY
t
idle(READY)
t
dis
t
stp(READY)
is only applicable after the t
en
delay.
Fig 19. t
stp(READY)
that can occur after t
en
002aab593
t
en
SCLIN
SCLOUT
SDAOUT
ENABLE
READY
t
stp(READY)
SDAIN
t
stp(READY)
is only applicable after the t
en
delay.
Fig 20. t
stp(READY)
delay that can occur after t
en
and t
idle(READY)
002aab594
t
en
t
idle(READY)
SCLIN, SDAIN,
SCLOUT, SDAOUT
ENABLE
READY
t
stp(READY)
PCA9513A_PCA9514A_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 18 August 2009 18 of 26
NXP Semiconductors
PCA9513A; PCA9514A
Hot swappable I
2
C-bus and SMBus bus buffer
12. Test information
R
L
= load resistor
C
L
= load capacitance includes jig and probe capacitance
R
T
= termination resistance should be equal to the output impedance Z
o
of the pulse generator
Fig 21. Test circuitry for switching times
PULSE
GENERATOR
V
O
C
L
100 pF
R
L
10 k
002aab595
R
T
V
I
V
CC
V
CC
DUT

PCA9513AD,112

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
Buffers & Line Drivers HOT SWAP I2C/SMBUS
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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