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MC74VHC139DR2

P1-P3P4-P6P7-P8
© Semiconductor Components Industries, LLC, 2004
August, 2004 − Rev. 3
1 Publication Order Number:
MC74VHC139/D
MC74VHC139
Dual 2−to−4 Decoder/
Demultiplexer
The MC74VHC139 is an advanced high speed CMOS 2−to−4
decoder/ demultiplexer fabricated with silicon gate CMOS
technology. It achieves high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining CMOS low power
dissipation.
When the device is enabled (E
= low), it can be used for gating or as
a data input for demultiplexing operations. When the enable input is
held high, all four outputs are fixed high, independent of other inputs.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7 V, allowing the interface of 5 V
systems to 3 V systems.
• High Speed: t
PD
= 5.0 ns (Typ) at V
CC
= 5 V
• Low Power Dissipation: I
CC
= 4 mA (Max) at T
A
= 25°C
• High Noise Immunity: V
NIH
= V
NIL
= 28% V
CC
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
• Designed for 2 V to 5.5 V Operating Range
• Low Noise: V
OLP
= 0.8 V (Max)
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300 mA
• ESD Performance: Human Body Model > 2000 V;
Machine Model > 200 V
• Chip Complexity: 100 FETs or 25 Equivalent Gates
• Pb−Free Packages are Available*
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
SOIC−16
D SUFFIX
CASE 751B
MARKING DIAGRAMS
1
8
9
16
1
8
16 9
1
16 9
8
VHC139
AWLYYWW
VHC
139
ALYW
74VHC139
ALYW
TSSOP−16
DT SUFFIX
CASE 948F
SOEIAJ−16
M SUFFIX
CASE 966
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
http://onsemi.com
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
ORDERING INFORMATION
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
Ea
A1a
A0a
GND
A1b
A0b
Eb
V
CC
Y0a
Y1a
Y2a
Y3a
Y0b
Y1b
Y2b
Y3b
PIN ASSIGNMENT
MC74VHC139
http://onsemi.com
2
Figure 1. Logic Diagram
A0a
A1a
Ea
A0b
A1b
1
Eb
Y0a
Y1a
Y2a
Y3a
Y0b
Y1b
Y2b
Y3b
ACTIVE−LOW
OUTPUTS
ADDRESS
INPUTS
ACTIVE−LOW
OUTPUTS
3
2
ADDRESS
INPUTS
13
14
15
4
5
6
7
12
11
10
9
Table 1. FUNCTION TABLE
Inputs Outputs
E A1 A0 Y0 Y1 Y2 Y3
H X X H H H H
L L L L H H H
L L H H L H H
L H L H H L H
L H H H H H L
En
A0
A1
Y0
Y1
Y2
Y3
Figure 2. Expanded Logic Diagram
(1/2 of Device)
INPUT
Figure 3. Input Equivalent Circuit
4
Figure 4. IEC Logic Diagram
Y0a
Y1a
Y2a
Y3a
Y0b
Y1b
Y2b
Y3b
5
6
7
12
11
10
9
15
14
13
1
2
3
A1a
A0a
Ea
A1b
A0b
Eb
2
1
EN
X/Y
1
0
2
3
0
1
DMUX
1
0
2
3
G
0
3
15
14
13
1
2
3
A1a
A0a
Ea
A1b
A0b
Eb
Y0a
Y1a
Y2a
Y3a
Y0b
Y1b
Y2b
Y3b
4
5
6
7
12
11
10
9
MC74VHC139
http://onsemi.com
3
MAXIMUM RATINGS
Symbol Parameter Value Unit
V
CC
DC Supply Voltage –0.5 to +7.0 V
V
in
DC Input Voltage –0.5 to +7.0 V
V
out
DC Output Voltage –0.5 to V
CC
+ 0.5 V
I
IK
Input Diode Current −20 mA
I
OK
Output Diode Current ±20 mA
I
out
DC Output Current, per Pin ±25 mA
I
CC
DC Supply Current, V
CC
and GND Pins ±75 mA
P
D
Power Dissipation in Still Air, SOIC Packages
†
TSSOP Package
†
500
450
mW
T
stg
Storage Temperature –65 to +150 °C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings
applied to the device are individual stress limit values (not normal operating conditions) and are
not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
†Derating − SOIC Packages: – 7 mW/°C from 65° to 125°C
TSSOP Package: − 6.1 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
CC
DC Supply Voltage 2.0 5.5 V
V
in
DC Input Voltage 0 5.5 V
V
out
DC Output Voltage 0 V
CC
V
T
A
Operating Temperature −55 +125 °C
t
r
, t
f
Input Rise and Fall Time V
CC
= 3.3 V ±0.3V
(Figure 3) V
CC
=5.0 V ±0.5V
0
0
100
20
ns/V
The q
JA
of the package is equal to 1/Derating. Higher junction temperatures may affect the
expected lifetime of the device per the table and figure below.
DEVICE JUNCTION TEMPERATURE VERSUS
TIME TO 0.1% BOND FAILURES
Junction
Temperature (°C)
Time, Hours Time, Years
80 1,032,200 117.8
90 419,300 47.9
100 178,700 20.4
110 79,600 9.4
120 37,000 4.2
130 17,800 2.0
140 8,900 1.0
1
1 10 100
1000
TIME, YEARS
NORMALIZED FAILURE RATE
T
J
= 80
C°
T
J
= 90
C°
T
J
= 100 C°
T
J
= 110 C°
T
J
= 130 C°
T
J
= 120 C°
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
Figure 5. Failure Rate vs. Time
Junction Temperature
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, V
in
and
V
out
should be constrained to the
range GND v (V
in
or V
out
) v V
CC
.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V
CC
).
Unused outputs must be left open.
P1-P3P4-P6P7-P8

MC74VHC139DR2

Mfr. #:
Buy MC74VHC139DR2
Manufacturer:
ON Semiconductor
Description:
IC DCODER/DMUX DUAL 2-4 16-SOIC
Lifecycle:
New from this manufacturer.
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