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CAT28LV64GI-25T

P1-P3P4-P6P7-P9P10-P12P13-P15
© Semiconductor Components Industries, LLC, 2009
October, 2009 − Rev. 7
1 Publication Order Number:
CAT28LV64/D
CAT28LV64
64 kb CMOS Parallel
EEPROM
Description
The CAT28LV64 is a low voltage, low power, CMOS Parallel
EEPROM organized as 8K x 8−bits. It requires a simple interface for
in−system programming. On−chip address and data latches,
self−timed write cycle with auto−clear and V
CC
power up/down write
protection eliminate additional timing and protection hardware. DATA
Polling and Toggle status bit signal the start and end of the self−timed
write cycle. Additionally, the CAT28LV64 features hardware and
software write protection.
The CAT28LV64 is manufactured using ON Semiconductor’s
advanced CMOS floating gate technology. It is designed to endure
100,000 program/erase cycles and has a data retention of 100 years.
The device is available in JEDEC approved 28−pin DIP, 28−pin TSOP,
28−pin SOIC or 32−pin PLCC packages.
Features
• 3.0 V to 3.6 V Supply
• Read Access Times:
– 150/200/250 ns
• Low Power CMOS Dissipation:
– Active: 8 mA Max.
– Standby: 100 mA Max.
• Simple Write Operation:
– On−chip Address and Data Latches
– Self−timed Write Cycle with Auto−clear
• Fast Write Cycle Time:
– 5 ms Max.
• Commercial, Industrial and Automotive Temperature Ranges
• CMOS and TTL Compatible I/O
• Automatic Page Write Operation:
– 1 to 32 bytes in 5 ms
– Page Load Timer
• End of Write Detection:
– Toggle bit
– DATA Polling
• Hardware and Software Write Protection
• 100,000 Program/Erase Cycles
• 100 Year Data Retention
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
http://onsemi.com
See detailed ordering and shipping information in the package
dimensions section on page 15 of this data sheet.
ORDERING INFORMATION
PDIP−28
P, L SUFFIX
CASE 646AE
PLCC−32
N, G SUFFIX
CASE 776AK
Address InputsA
0
−A
12
Data Inputs/OutputsI/O
0
−I/O
7
Chip EnableCE
Output EnableOE
Write EnableWE
3.0 V to 3.6 V SupplyV
CC
FunctionPin Name
PIN FUNCTION
SOIC−28
J, K, W, X SUFFIX
CASE 751BM
GroundV
SS
No ConnectNC
TSOP−28
H13 SUFFIX
CASE 318AE
CAT28LV64
http://onsemi.com
2
PIN CONFIGURATIONS
5
7
6
10
9
12
11
8
13
14 15 16 17 18 19 20
4 3 2 1 32 31 30
29
27
28
24
25
22
23
26
21
A
8
A
9
A
11
NC
OE
A
10
CE
I/O
7
I/O
6
A
7
A
12
NC
NC
V
CC
WE
NC
A
6
A
5
A
4
A
3
A
2
A
1
A
0
NC
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
V
SS
NC
PLCC Package (N, G)
DIP Package (P, L) SOIC Package (J, K, W, X)
5
4
7
6
3
2
1
10
9
12
11
8
22
23
20
21
24
25
26
17
18
15
16
19
14
13
27
28
5
4
7
6
3
2
1
10
9
12
11
8
22
23
20
21
24
25
26
17
18
15
16
19
14
13
27
28
TSOP Package (8 mm x 13.4 mm) (H13)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
OE
A
11
A
9
A
8
WE
V
CC
NC
NC
NC
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
V
SS
WE
V
CC
NC
A
8
A
9
A
11
OE
A
10
CE
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
NC
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
V
SS
WE
V
CC
NC
A
8
A
9
A
11
OE
A
10
CE
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
A
12
A
7
A
6
A
5
A
4
A
3
A
10
CE
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
GND
I/O
2
I/O
1
I/O
0
A
0
A
1
A
2
(Top Views)
CAT28LV64
http://onsemi.com
3
Figure 1. Block Diagram
CE
OE
WE
V
CC
A
0
−A
4
A
5
−A
12
DATA POLLING
AND
TOGGLE BIT
I/O
0
−I/O
7
ADDR. BUFFER
& LATCHES
ADDR. BUFFER
& LATCHES
INADVERTENT
CONTROL
LOGIC
TIMER
HIGH VOLTAGE
GENERATOR
I/O BUFFERS
32 BYTE PAGE
REGISTER
WRITE
PROTECTION
ROW
DECODER
COLUMN
DECODER
8,192 x 8
E
2
PROM
ARRAY
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters Ratings Units
Temperature Under Bias −55 to +125 °C
Storage Temperature −65 to +150 °C
Voltage on Any Pin with Respect to Ground (Note 1) −2.0 V to +V
CC
+ 2.0 V V
V
CC
with Respect to Ground −2.0 to +7.0 V
Package Power Dissipation Capability (T
A
= 25°C) 1.0 W
Lead Soldering Temperature (10 secs) 300 °C
Output Short Circuit Current (Note 2) 100 mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The minimum DC input voltage is −0.5 V. During transitions, inputs may undershoot to −2.0 V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+ 0.5 V, which may overshoot to V
CC
+ 2.0 V for periods of less than 20 ns.
2. Output shorted for no more than one second. No more than one output shorted at a time.
Table 2. RELIABILITY CHARACTERISTICS (Note 3)
Symbol Parameter Test Method Min Max Units
N
END
Endurance MIL−STD−883, Test Method 1033 10
5
Cycles/Byte
T
DR
Data Retention MIL−STD−883, Test Method 1008 100 Years
V
ZAP
ESD Susceptibility MIL−STD−883, Test Method 3015 2,000 V
I
LTH
(Note 4) Latch−Up JEDEC Standard 17 100 mA
3. These parameters are tested initially and after a design or process change that affects the parameters.
4. Latch−up protection is provided for stresses up to 100 mA on address and data pins from −1 V to V
CC
+ 1 V.
Table 3. MODE SELECTION
Mode CE WE OE I/O Power
Read L H L D
OUT
ACTIVE
Byte Write (WE Controlled) L H D
IN
ACTIVE
Byte Write (CE Controlled) L H D
IN
ACTIVE
Standby and Write Inhibit H X X High−Z STANDBY
Read and Write Inhibit X H H High−Z ACTIVE
P1-P3P4-P6P7-P9P10-P12P13-P15

CAT28LV64GI-25T

Mfr. #:
Buy CAT28LV64GI-25T
Manufacturer:
ON Semiconductor
Description:
EEPROM 64K-Bit CMOS PARA EEPROM
Lifecycle:
New from this manufacturer.
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