LTC2902-2CGN#TRPBF Datasheet LTC2902-1CGN#PBF, LTC2902-2CGN#PBF, LTC2902-2IGN#PBF | P10-P12

LTC2902

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Power-Up

On power-up, the larger of V1 or V2 will power the drive

circuits for the RST and the COMPX pins. This ensures

that the RST and COMPX outputs will be low as soon as

V1 or V2 reaches 1V. The RST and COMPX outputs will

remain low until the part is programmed. After program-

ming, if any one of the V

inputs is below its programmed

threshold, RST will be a logic low. Once all the V

inputs

rise above their thresholds, an internal timer is started

and RST is released after the programmed delay time. If

< (V3 – 1) and V

< 2.4V, the V3 input impedance

will be low (1kΩ typ).

Monitor Programming

The LTC2902 input voltage combination is selected by

placing the recommended resistor divider from V

REF

GND and connecting the tap point to V

, as shown in

Figure 4. Table 1 offers recommended 1% resistor values

for the various modes. The last column in Table 1 speci-

fies optimum V

REF

ratios (±0.01) to be used when

pro

gramming with a ratiometric DAC.

During power-up, once V1 or V2 reaches 2.4V (max), the

monitor enters a programming period of approximately

150µs during which the voltage on the V

pin is sampled

and the monitor is configured to the desired input combi-

nation. Do not add capacitance to the V

pin. Immediately

after programming, the comparators are enabled and

supply monitoring will begin.

Supply Monitoring

The LTC2902 is a low power, high accuracy program-

mable quad supply monitoring circuit with four nondelayed

monitor outputs, a common reset output and selectable

supply thresholds. Reset timing is adjustable using an

external capacitor. Single pin programming selects 1 of 16

input voltage monitor combinations. Two digital inputs

select one of four supply tolerances (5%, 7.5%, 10% or

12.5%). All four voltage inputs must be above predeter-

mined thresholds for the reset not to be invoked. The

LTC2902 will assert the reset and comparator outputs

during power-up, power-down and brownout conditions

on any one of the voltage inputs.

Table 1. Voltage Threshold Programming

MODE V1 (V) V2 (V) V3 (V) V4 (V) R1 (kΩ) R2 (kΩ)V

REF

0 5.0 3.3 ADJ ADJ Open Short 0.000

1 5.0 3.3 ADJ –ADJ 93.1 9.53 0.094

2 3.3 2.5 ADJ ADJ 86.6 16.2 0.156

3 3.3 2.5 ADJ –ADJ 78.7 22.1 0.219

4 3.3 2.5 1.5 ADJ 71.5 28.0 0.281

5 5.0 3.3 2.5 ADJ 66.5 34.8 0.344

6 5.0 3.3 2.5 1.8 59.0 40.2 0.406

7 5.0 3.3 2.5 1.5 53.6 47.5 0.469

8 5.0 3.0 2.5 ADJ 47.5 53.6 0.531

9 5.0 3.0 ADJ ADJ 40.2 59.0 0.594

10 3.3 2.5 1.8 1.5 34.8 66.5 0.656

11 3.3 2.5 1.8 ADJ 28.0 71.5 0.719

12 3.3 2.5 1.8 –ADJ 22.1 78.7 0.781

13 5.0 3.3 1.8 –ADJ 16.2 86.6 0.844

14 5.0 3.3 1.8 ADJ 9.53 93.1 0.906

15 5.0 3.0 1.8 ADJ Short Open 1.000

Figure 4. Monitor Programming

2902 F04

REF

GND

LTC2902

The inverting inputs on the V3 and/or V4 comparators are

set to 0.5V when the positive adjustable modes are selected

and with T0 and T1 low (5% tolerance) (Figure 5). The tap

point on an external resistive divider, connected between

the positive voltage being sensed and ground, is connected

to the high impedance noninverting inputs (V3, V4). The

trip voltage is calculated from:

TRIP













05 1

Once the resistor divider is set in the 5% tolerance mode,

there is no need to change the divider for the other

tolerance modes (7.5%, 10%, 12.5%) because the inter-

nal reference is scaled accordingly, moving the trip point

in –2.5% increments.

LTC2902

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In the negative adjustable mode, the noninverting input on

the V4 comparator is connected to ground (Figure 6). The

tap point on an external resistive divider, connected be-

tween the negative voltage being sensed and the V

REF

pin,

is connected to the high impedance inverting input (V4).

REF

provides the necessary level shift required to operate

at ground. The trip voltage is calculated from:

TRIP REF REF













=–;.

1 210

T0,T1 Low (5% Tolerance Mode)

Once the resistor divider is set in the 5% tolerance mode,

there is no need to change the divider for the other

tolerance modes (7.5%, 10%, 12.5%) because V

REF

scaled accordingly, moving the trip point in –2.5%

increments.

In a negative adjustable application, the minimum value

for R4 is limited by the sourcing capability of V

REF

(±1mA).

With no other load on V

REF

, R4 (minimum) is:

1.21V ÷ 1mA = 1.21kΩ

Tables 2 and 3 offer suggested 1% resistor values for

various adjustable applications.

Although all four supply monitor comparators have built-in

glitch immunity, bypass capacitors on V1 and V2 are

recommended because the greater of V1 or V2 is also the

for the chip. Filter capacitors on the V3 and V4 inputs

are allowed.

Power-Down

On power-down, once any of the V

inputs drop below

their threshold, RST and COMPX are held at a logic low.

A logic low of 0.4V is guaranteed until both V1 and V2

drop below 1V. If the bandgap reference becomes invalid

< 2V typ), the part will reprogram once V

rises

above 2.4V (max).

Monitor Output Rise and Fall Time Estimation

All of the outputs (RST, COMPX) have strong pull-down

capability. If the external load capacitance (C

LOAD

) for a

Table 2. Suggested 1% Resistor Values for the ADJ Inputs

SUPPLY

(V) V

TRIP

(V) R3 (kΩ) R4 (kΩ)

12 11.25 2150 100

10 9.4 1780 100

8 7.5 1400 100

7.5 7 1300 100

6 5.6 1020 100

5 4.725 845 100

3.3 3.055 511 100

3 2.82 464 100

2.5 2.325 365 100

1.8 1.685 237 100

1.5 1.410 182 100

1.2 1.120 124 100

1 0.933 86.6 100

0.9 0.840 68.1 100

Table 3. Suggested 1% Resistor Values for the –ADJ Input

SUPPLY

(V) V

TRIP

(V) R3 (kΩ) R4 (kΩ)

–2 –1.87 187 121

–5 –4.64 464 121

–5.2 –4.87 487 121

–10 –9.31 931 121

–12 –11.30 1130 121

Figure 5. Setting the Positive Adjustable Trip Point

Figure 6. Setting the Negative Adjustable Trip Point

–

2902 F06

REF

TRIP

LTC2902

–

0.5V

5% TOLERANCE MODE

2902 F05

V3 OR V4

TRIP

LTC2902

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APPLICATIO S I FOR ATIO

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particular output is known, output fall time (10% to 90%)

is estimated using:

FALL

≈ 2.2 • R

• C

LOAD

where R

is the on-resistance of the internal pull-down

transistor. The typical performance curve (V

vs I

SINK

)

demonstrates that the pull-down current is somewhat

linear versus output voltage. Using the 25°C curve, R

estimated to be approximately 40Ω. Assuming a 150pF

load capacitance, the fall time is about 13.2ns.

Although the outputs are considered to be “open-drain,”

they do have a weak pull-up capability (see COMPX or RST

Pull-Up Current vs V2 curve). Output rise time (10% to

90%) is estimated using:

RISE

≈ 2.2 • R

• C

LOAD

where R

is the on-resistance of the pull-up transistor.

The on-resistance as a function of the V2 voltage at room

temperature is estimated using:

=Ω

610

•

–

with V2 = 3.3V, R

is about 260k. Using 150pF for load

capacitance, the rise time is 86µs. If the output needs to

pull up faster and/or to a higher voltage, a smaller

external pull-up resistor may be used. Using a 10k pull-

up resistor, the rise time is reduced to 3.3µs for a 150pF

load capacitance.

The LTC2902-2 has an active pull-up to V2 on the RST

output. The typical performance curve (RST Pull-Up Cur-

rent vs V2 curve) demonstrates that the pull-up current is

somewhat linear versus the V2 voltage and R

is esti-

mated to be approximately 625Ω. A 150pF load capaci-

tance makes the rise time about 206ns.

Selecting the Reset Timing Capacitor

The reset time-out period is adjustable in order to accom-

modate a variety of microprocessor applications. The

reset time-out period, t

RST

, is adjusted by connecting a

capacitor, C

, between the CRT pin and ground. The value

of this capacitor is determined by:

= t

RST

• 217 • 10

–9

with C

in Farads and t

RST

in seconds. The C

value per

millisecond of delay can also be expressed as C

/ms =

217 (pF/ms).

Leaving the CRT pin unconnected will generate a mini-

mum reset time-out of approximately 50µs. Maximum

reset time-out is limited by the largest available low

leakage capacitor. The accuracy of the time-out period will

be affected by capacitor leakage (the nominal charging

current is 2µA) and capacitor tolerance. A low leakage

ceramic capacitor is recommended.

Tolerance Programming and the RESET Disable

Using the two digital inputs T0 and T1, the user can

program the global supply tolerance for the LTC2902 (5%,

7.5%, 10%, 12.5%). The larger tolerances provide more

headroom by lowering the trip thresholds.

Table 4. Tolerance Programming

T0 T1 TOLERANCE (%) V

REF

(V)

Low Low 5 1.210

Low High 7.5 1.178

High Low 10 1.146

High High 12.5 1.113

Under conventional operation, RST and COMPX will go

low when V

is below its threshold. At any time, the RDIS

pin can be pulled low, overriding the reset operation and

forcing the RST pin high. This feature is useful when

determining supply margins under processor control since

the reset command will not be invoked. The RDIS pin is

connected to a weak internal pull-up to V

(10µA typ),

allowing the pin to be left floating if unused.

Ensuring RST Valid for V

Down to 0V (LTC2902-2)

When V

is below 1V the RST pull-down capability is

drastically reduced. The RST pin may float to undeter-

mined voltages when connected to high impedance (such

as CMOS logic inputs). The addition of a pull-down resis-

tor from RST to ground will provide a path for stray charge

and/or leakage currents. The resistor value should be

small enough to provide effective pull-down without ex-

cessively loading the pull-up circuitry. Too large a value

may not pull down well enough. A 100k resistor from RST

to ground is satisfactory for most applications.

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LTC2902-2CGN#TRPBF

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Manufacturer:

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Description:

Supervisory Circuits Quad Monitor w/RST Disable, TOL Select

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LTC2902-2CGN#TRPBF

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