89HPES10T4G2ZABC8 Datasheet 89HPES10T4G2ZBBCG, 89HPES10T4G2ZBBCGI, 89HPES10T4G2ZBBCG8 | P7-P9

7 of 30 May 10, 2016

IDT 89HPES10T4G2 Data Sheet

JTAG_TDO O JTAG Data Output. This is the serial data shifted out from the boundary

scan logic or JTAG Controller. When no data is being shifted out, this signal

is tri-stated.

JTAG_TMS I JTAG Mode. The value on this signal controls the test mode select of the

boundary scan logic or JTAG Controller.

JTAG_TRST_N I JTAG Reset. This active low signal asynchronously resets the boundary

scan logic and JTAG TAP Controller. An external pull-up on the board is

recommended to meet the JTAG specification in cases where the tester

can access this signal. However, for systems running in functional mode,

one of the following should occur:

1) actively drive this signal low with control logic

2) statically drive this signal low with an external pull-down on the board

Signal Type Name/Description

REFRES0 I/O Port 0 External Reference Resistor. Provides a reference for the Port 0

SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resis-

tor should be connected from this pin to ground.

REFRES2 I/O Port 2 External Reference Resistor. Provides a reference for the Port 2

SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resis-

tor should be connected from this pin to ground.

REFRES4 I/O Port 4 External Reference Resistor. Provides a reference for the Port 4

SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resis-

tor should be connected from this pin to ground.

REFRES6 I/O Port 6 External Reference Resistor. Provides a reference for the Port 6

SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resis-

tor should be connected from this pin to ground.

CORE I Core V

DD.

Power supply for core logic.

I/O I I/O V

DD.

LVTTL I/O buffer power supply.

PEA I PCI Express Analog Power. Serdes analog power supply (1.0V).

PEHA I PCI Express Analog High Power. Serdes analog power supply (2.5V).

PETA I PCI Express Transmitter Analog Voltage. Serdes transmitter analog

power supply (1.0V).

I Ground.

Table 7 Power, Ground, and SerDes Resistor Pins

Signal Type Name/Description

Table 6 Test Pins (Part 2 of 2)

8 of 30 May 10, 2016

IDT 89HPES10T4G2 Data Sheet

Pin Characteristics

Note: Some input pads of the PES10T4G2 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate

levels. This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, any input pin left

floating can cause a slight increase in power consumption.

Function Pin Name Type Buffer

I/O

Type

Internal

Resistor

Notes

PCI Express Inter-

face

PE0RN[3:0] I PCIe

differential

Serial Link

PE0RP[3:0] I

PE0TN[3:0] O

PE0TP[3:0] O

PE2RN[1:0] I

PE2RP[1:0] I

PE2TN[1:0] O

PE2TP[1:0] O

PE4RN[1:0] I

PE4RP[1:0] I

PE4TN[1:0] O

PE4TP[1:0] O

PE6RN[1:0] I

PE6RP[1:0] I

PE6TN[1:0] O

PE6TP[1:0] O

PEREFCLKN[0] I HCSL Diff. Clock

Input

Refer to Table 9

PEREFCLKP[0] I

REFCLKM I LVTTL Input pull-down

SMBus MSMBADDR[4:1] I LVTTL Input pull-up

MSMBCLK I/O STI

pull-up on board

MSMBDAT I/O STI pull-up on board

SSMBADDR[5,3:1] I Input pull-up

SSMBCLK I/O STI pull-up on board

SSMBDAT I/O STI pull-up on board

General Purpose I/O GPIO[11,7:0] I/O LVTTL STI,

High Drive

pull-up

System Pins CCLKDS I LVTTL Input pull-up

CCLKUS I Input pull-up

MSMBSMODE I Input pull-down

PERSTN I STI

RSTHALT I Input pull-down

SWMODE[2:0] I Input pull-down

Table 8 Pin Characteristics (Part 1 of 2)

9 of 30 May 10, 2016

IDT 89HPES10T4G2 Data Sheet

EJTAG / JTAG JTAG_TCK I LVTTL STI pull-up

JTAG_TDI I STI pull-up

JTAG_TDO O

JTAG_TMS I STI pull-up

JTAG_TRST_N I STI pull-up

SerDes Reference

Resistors

REFRES0 I/O Analog

REFRES2 I/O

REFRES4 I/O

REFRES6 I/O

Internal resistor values under typical operating conditions are 92K  for pull-up and 90K for pull-down.

All receiver pins set the DC common mode voltage to ground. All transmitters must be AC coupled to the media.

Schmitt Trigger Input (STI).

Function Pin Name Type Buffer

I/O

Type

Internal

Resistor

Notes

Table 8 Pin Characteristics (Part 2 of 2)

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30

89HPES10T4G2ZABC8

Mfr. #:

Buy 89HPES10T4G2ZABC8

Manufacturer:

Description:

PCI Interface IC PCI EXPRESS SWITCH

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

89HPES10T4G2ZABC8

89HPES10T4G2ZABC8

Products related to this Datasheet