NCP1596A
http://onsemi.com
10
DETAILED OPERATING DESCRIPTION
Introduction
The NCP1596A is a current−mode buck converter with
switching frequency at 1.5 MHz. High operation frequency
can reduce the capacitor value and PCB area. Also, more
features are built in this converter.
1. Internal 1 ms soft−start to avoid inrush current at
startup.
2. Internal cycle by cycle current limit provides an
output short circuit protection.
3. Internal compensation. No external compensation
components are necessary.
4. Thermal shutdown protects the devices from over
heat.
5. 100% duty cycle allowed. Speed up transient load
response.
The upper feature can provide more cost effective
solutions to applications. A simple function block diagram
and timing diagram are shown in Figure 1 and Figure 2.
Soft−Start and Current Limit
A soft start circuit is internally implemented to reduce the
in−rush current during startup. This helps to reduce the
output voltage over−shoot.
The current limit is set to allow peak switch current in
excess of 2 A. The intended output current of the system is
1.5 A. The ripple current is calculated to be approximately
350 mA with a 3.3 mH inductor. Therefore, the peak current
at 1.5 A output will be approximately 1.7 Amps. A 2.5 Amp
set point will allow for transient currents during load step.
The current limit circuit is implemented as a cycle−by−cycle
current limit. Each on−cycle is treated as a separate situation.
Current limiting is implemented by monitoring the
P−channel switch current buildup during conduction with a
current limit comparator. The output of the current limit
comparator resets the PWM latch, immediately terminating
the current cycle. When output loading is short circuit,
device will auto restart with soft−start.
Error Amplifier and Slope Compensation
A fully internal compensated error amplifier is provided
inside NCP1596A. No external circuitry is needed to
stabilize the device. The error amplifier provides an error
signal to the PWM comparator by comparing the feedback
voltage (800 mV) with internal voltage reference of 1.2 V.
Current mode converter can exhibit instability at duty
cycles over 50%. A slope compensation circuit is provided
inside NCP1596A to overcome the potential instability.
Slope compensation consists of a ramp signal generated by
the synchronization block and adding this to the inductor
current signal. The summed signal is then applied to the
PWM comparator.
Thermal Shutdown
Internal Thermal Shutdown circuitry is provided to
protect the integrated circuit in the event when maximum
junction temperature is exceeded. When activated, typically
at 180°C, the shutdown signal will disable the P−channel
switch. The thermal shutdown circuit is designed with 30°C
of hysteresis. This means that the switching will not start
until the die temperature drops by this amount. This feature
is provided to prevent catastrophic failures from accidental
device overheating. It is not intended as a substitute for
proper heat sinking. NCP1596A is contained in the
thermally enhanced QFN package.
Under Voltage Lockout (UVLO)
UVLO function is used to ensure the logic level correctly
when input voltage is very low. In NCP1596A, the UVLO
level is set to 3.5 V. If the input voltage is less than 3.5 V, the
converter will shutdown itself automatically.
Low Power Shutdown Mode (EN)
NCP1596A can be disabled whenever the EN pin is tied
to ground. During the shutdown mode, the internal
reference, oscillator and driver control circuits will be turn
off, the device only consume 1 mA typically and output
voltage will be discharge to zero by the external resistor
divider. EN pin has an internal pull−up current source, which
typical value is 500 nA.
Power Saving Pulse−Frequency−Modulation (PFM)
Control Scheme
While the converter loading decreases, the converter
enters the Discontinues−conduction−mode (DCM)
operation. In DCM operation, the on−time (T
on
) of the
integrated switch for each switching cycle will decrease
when the output current decreases. In order to maintain a
high converter efficiency at light load condition. A
minimum T
on
is set to 70 ns. It can make sure a minimum
fixed power send to output. To avoid a higher switch loss
occurs when without loading apply. This control scheme can
reduce the switching loss at light load and improve the
conversion efficiency.
