IDT80KSW0002 Datasheet
CPS-16 Datasheet 47 April 6, 2016
Pin Summary
Pin
Name
Function Supply / Interface Pin Function Description
ADS I
2
C(VDD, GND) / CMOS Input I
2
C address width select. Set ADS = GND for 7-bit CPS-16 slave
address. ADS = Vdd for 10-bit. NOTE: SUPPLY / LEVELS
REQUIREMENTS ARE UNIQUE FROM THE OTHER I
2
C PINS.
DNC Do Not Connect. This pin should be left FLOATING. It should not
be connected to any other signal or power rail.
GND Digital Ground
(CMOS)
Digital GND. All pins must be tied to single potential power supply
ground plane.
GNDS Analog Ground
(CMOS)
Analog GND. All pins must be tied to single potential ground sup-
ply plane.
ID0 - ID9 I
2
C(VDD, GND) / CMOS Input I
2
C Slave ID addresses. This should be set statically to Vdd or
GND at power-up. NOTE: SUPPLY / LEVELS REQUIREMENTS
ARE UNQUE FROM THE OTHER I
2
C PINS.
NC Not connected
MM I
2
C CMOS Input Select the I
2
C Mater or Slave mode. Logic high for Master mode
IRQ
Interrupt (VDD3, GND) / CMOS Output This is an interrupt output pin whose value is given by the Error
Management Block.
REF_CLK +/- SERDES Clock (V
DD, GND) / Differential Input Differential input clock. This clock is used as the 156.25 MHz refer-
ence for standard SERDES operation.
REXTN,
REXTP
Rext External bias resistor. Rextn must be connected to Rextp with a
12k Ohm resistor. This establishes the drive bias on the SERDES
output. This provides CML driver stability across process and tem-
perature.
RST
Reset (VDD3, GND) / CMOS Input CPS-16 Global Reset. Sets all internal registers to default values.
Resets all PLLs. Resets all port configurations. This is a HARD
Reset.
RX0+/- to
RX15+/-
sRIO Receive (V
DDS, GNDS) / RIO Differential Input Differential receiver inputs, Lanes 0 to 15
SCL I
2
C(VDD3, GND) / CMOS IO I
2
C Clock.
SDA I
2
C(VDD3, GND) / CMOS IO I
2
C Serial Data IO. Data direction is determined by the I
2
C Read/
Write bit. See I
2
C section for further detail.
SPD[1:0] SPD (V
DD, GND) / CMOS Input Speed Select Pins. These pins define sRIO port speed at RESET
for all ports. The RESET setting may be overridden by subsequent
programming of the QUAD_CTRL register. SPD[1:0] = {00 =
1.25G, 01 = 2.5G, 10 = 3.125G, 11 = RESERVED}. These pins
must remain STATICALLY BIASED before power-up.
TCK JTAG (V
DD3, GND) / CMOS Input JTAG Tap Port Clock
TDI JTAG (V
DD3, GND) / CMOS Input JTAG Tap Port Input
TDO JTAG (V
DD3, GND) / CMOS Output JTAG Tap Port Output
TMS JTAG (V
DD3, GND) / CMOS Input JTAG Tap Port Mode Select
TRST
JTAG (VDD3, GND) / CMOS Input JTAG Tap Port Asynchronous Reset
Table 36 Pin Summary (Alphabetical)
