MAX848/MAX849
1-Cell to 3-Cell, High-Power,
Low-Noise, Step-Up DC-DC Converters
10 ______________________________________________________________________________________
Low-Power PFM Mode
When CLK/SEL is pulled low, the MAX848/MAX849 oper-
ate in low-power, low-supply-current PFM mode. Pulse-
frequency modulation provides the highest efficiency at
light loads. The P-channel rectifier is turned off to reduce
gate-charge losses, and the regulator operates in dis-
continuous mode. The N-channel power MOSFET is kept
on until the inductor current ramps to 30% of the current
limit. The inductor energy is delivered to the output
capacitor when the switch turns off. A new cycle is inhib-
ited until the inductor current crosses zero. Zero current
detection is accomplished by sensing the LX voltage
crossing the output voltage. Figure 3 shows the block
diagram for the PFM controller.
Low-Noise PWM Mode
When CLK/SEL is pulled high, the MAX848/MAX849
operate in high-power, low-noise, current-mode PWM,
switching at the 300kHz nominal internal oscillator fre-
quency. The internal rectifier is active in this mode,
and the regulator operates in continuous mode. The
N-channel power MOSFET turns on until either the output
voltage is in regulation or the inductor current limit is
reached (0.8A for the MAX848 and 1.4A for the
MAX849). The switch turns off for the remainder of the
cycle and the inductor energy is delivered to the output
capacitor. A new cycle is initiated on the next oscillator
cycle. In low-noise applications, the fundamental and the
harmonics generated by the fixed switching frequency
can easily be filtered. Figure 4 shows the block diagram
for the PWM controller.
The MAX848/MAX849 enter synchronized current-mode
PWM when a clock signal (200kHz < f
CLK
< 400kHz) is
applied to CLK/SEL. The internal synchronous rectifier
is active and the switching frequency is synchronized
to the externally applied clock signal. For wireless
applications, this ensures that the harmonics of the
switching frequencies are predictable and can be kept
outside the IF band(s). High-frequency operation per-
mits low-magnitude output ripple voltage.
The MAX848/MAX849 are capable of providing a stable
output even with a rapidly pulsing load (GSM, DECT),
such as from a transmitter power amplifier in digital cord-
less phones (see
Typical Operating Characteristics
).
In PWM mode, the use of the synchronous rectifier
ensures constant-frequency operation, regardless of
the load current.
Setting the Output Voltage Externally
The MAX848/MAX849 feature Dual Mode operation.
The output voltage is preset to 3.3V (FB = 0V), or it can
be adjusted from 2.7V to 5.5V with external resistors
R1, R2, and R3, as shown in Figure 5. To set the output
voltage externally, select resistor R3 in the 10k to
100k range. The values for R1 and R2 are given by:
R2 = R3(V
OUT
/ V
TRIP
- 1)
R1 = (R3 + R2)(V
TRIP
/ V
REF
- 1)
MAX849
C5
0.1µF
V
IN
= 1.1V
C2
0.1µF
C3
0.22µF
C1
22µF
OUT
GND
POK
ON1
ON2
CLK/SEL
REF
PGND
FB
POKIN
LX
POUT
C4
2 x 100µF
L1
10µH
D1
MBR0520L
3.3V @
200mA
R3
100k
10
*
HEAVY LINES INDICATE
HIGH-CURRENT PATH.
*
Figure 2. 3.3V Preset Output
Table 2. Selecting Operating Mode
CLK/SEL MODE
0 PFM
1 PWM
External clock
(200kHz ~ 400kHz)
Synchronized PWM
R
S
Q
R
DQ
PFM-MODE
CURRENT-
LIMIT LEVEL
REF
FEEDBACK
POUT
LX
PGND
LOGIC HIGH
N
CURRENT
SENSE
Figure 3. Controller Block Diagram in PFM Mode
MAX848/MAX849
1-Cell to 3-Cell, High-Power,
Low-Noise, Step-Up DC-DC Converters
______________________________________________________________________________________ 11
where V
REF
= 1.25V, V
OUT
is the desired output volt-
age, and V
TRIP
is the desired trip level for the power-
good comparator.
Power-OK
The MAX848/MAX849 feature a power-good compara-
tor. This comparator’s open-drain output, POK, is
pulled low when the output voltage falls below the nom-
inal internal threshold level of 3V with POKIN = 0V. To
set the power-good trip level externally, refer to the
Setting the Output Voltage Externally
section.
Analog-to-Digital Converter (ADC)
The MAX848/MAX849 have an internal, two-channel, seri-
al ADC. The ADC converts an analog input voltage into a
digital stream available at the DATA pin. The converter
skips clock pulses in proportion to the input voltage.
Output format is a return-to-zero bit stream with a bit
duration of 1/f
CLK
. At zero-scale input voltage, all pulses
are skipped and DATA remains low; with a positive full-
scale input voltage, no pulses are skipped; and at mid-
scale, every other pulse is skipped. The ADC’s clock is
one-half of the externally applied clock signal or one-half
of the internal 300kHz clock available at LX. In PFM
mode, the converter is not active and DATA is driven low.
Channel 1, AIN1, has an input voltage range of 0.625V
to 1.875V and is selected when AINSEL is low. Channel
2, AIN2, accepts inputs in the 0V to 2.5V range and is
selected when AINSEL is pulled high (Figure 6).
The ADC is a switched-capacitor type; therefore, an
anti-aliasing filter might be required at the inputs. Insert
a 1kseries resistor and a 0.01µF filter capacitor in
noisy environments.
Timer Function Implementation
Implement the necessary counter functions either with
discrete hardware or with microcontroller (µC) imple-
mentations. The output resolution depends on how
many of the ADC clock pulses are counted, as shown
in Figure 7.
Hardware Implementation
A complete hardware solution can be implemented
using either two counters or an ASIC. Resolution
depends on how many pulses are counted. The main
advantage of the discrete hardware implementation is
that accuracy is not affected by interrupt latency asso-
ciated with the µC solution.
R
S
Q
OSC
PWM-MODE
CURRENT-
LIMIT LEVEL
REF
FEEDBACK
POUT
LX
PGND
N
P
Figure 4. Controller Block Diagram in PWM Mode
MAX848
MAX849
OUT
POKIN
FB
POK
GND
OUTPUT
R1
R2
R3
Figure 5. Adjustable Output Voltage and Power-Good Trip Level
C/2
C/2
C
REF
C
D Q
÷2
2 x REF
AIN2
OSC
AINSEL
AIN1
DATA
Figure 6. A/D Converter Block Diagram
MAX848/MAX849
1-Cell to 3-Cell, High-Power,
Low-Noise, Step-Up DC-DC Converters
12 ______________________________________________________________________________________
When using two counters of the same length, as shown
in Figure 8, one counter (A) just counts the A/D clock
pulses (f
OSC
/2), and the other counter (B) counts DATA
output pulses. When counter A overflows (for example,
after 256 clock cycles for an 8-bit counter), counter B is
disabled. The controller reads the counter B output
data and calculates the analog voltage present at the
ADC’s input.
All µC Implementation
This implementation uses a µC timer and a counter.
The timer and the counter are reset at the same time.
The counter counts data-output pulses applied at its
input. When the timer times out, an interrupt is assert-
ed. The µC then reads the state of the counter register.
The interrupt-handling overhead can cause the counter
to count more pulses than desired. Accuracy depends
on how long the µC needs to read the counter. No
errors will occur if the counter is disabled within one
clock period. Interrupt latency reduces accuracy. The
main advantage of this implementation is that no exter-
nal hardware is required.
__________________Design Procedure
Inductor Selection
The MAX848/MAX849’s high switching frequency allows
the use of a small inductor. Use a 10µH inductor for the
MAX849 and a 22µH inductor for the MAX848. Inductors
with a ferrite core or equivalent are recommended; pow-
der iron cores are not recommended for use with high
switching frequencies. Make sure the inductor’s satura-
tion rating (the current at which the core begins to satu-
rate and inductance starts to fall) exceeds the internal
current limit: 0.8A for the MAX848 and 1.4A for the
MAX849. However, it is generally acceptable to bias the
inductor into saturation by approximately 20% (the point
where the inductance is 20% below the nominal value).
For highest efficiency, use a coil with low DC resistance,
preferably under 100m. To minimize radiated noise,
use a toroid, pot core, or shielded inductor. See Table 5
for a list of suggested inductor suppliers.
Diode Selection
The MAX848/MAX849’s high switching frequency
demands a high-speed rectifier. Schottky diodes, such
as the 1N5817 or MBR0520L, are recommended. Make
sure the diode’s current rating exceeds the maximum
load current and that its breakdown voltage exceeds
V
OUT
.
The Schottky rectifier diode carries load currents only in
the PFM operating mode, since the P-channel synchro-
nous rectifier is disabled. Therefore, the current rating
need not be high (0.5A is sufficient). In PFM mode, the
voltage drop across the rectifier diode causes efficien-
cy loss. However, when operating in PWM mode, the
internal P-channel synchronous rectifier is active and
efficiency loss due to the rectifier diode is minimized.
For high-temperature applications, Schottky diodes
may be inadequate due to their high leakage currents;
use high-speed silicon diodes such as the MUR105 or
EC11FS1. At heavy loads and high temperatures, the
benefits of a Schottky diode’s low forward voltage may
outweigh the disadvantage of high leakage current.
See Table 4 for a list of suggested diode suppliers.
f
OSC
/2
DATA
GIVES YOU 2-BIT RESOLUTION
COUNTING FOUR PULSES
Figure 7. Bit Stream at 1/2 Full Scale
EN
CLR
CLK RC8-BIT COUNTER
CLR
CLK
EN8-BIT COUNTER
LATCH
÷2
V
CC
CLOCK/SEL
OR LX
CLEAR
CARRY OUTPUT
DATA OUTPUT
A
B
Figure 8. Discrete Hardware Solution for Counting A/D Output
Data Pulses

MAX848ESE+T

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Maxim Integrated
Description:
Switching Voltage Regulators 1-3 Cell Step-Up DC/DC Converter
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