7
LT1614
OPERATIO
U
When Q1 turns off during the second phase of switching,
the SWX node voltage abruptly increases to (V
IN
+ |V
OUT
|).
The SW node voltage increases to V
D
(about 350mV). Now
current in the first loop, begining at C1, flows through L1,
C2, D1 and back to C1. Current in the second loop flows
from C3 through L2, D1 and back to C3. Load current
continues to be supplied by L2 and C3.
An important layout issue arises due to the chopped
nature of the currents flowing in Q1 and D1. If they are both
tied directly to the ground plane before being combined,
switching noise will be introduced into the ground plane.
It is almost impossible to get rid of this noise, once present
in the ground plane. The solution is to tie D1’s cathode to
the ground pin of the LT1614 before the combined cur-
rents are dumped into the ground plane as drawn in
Figures 4, 5 and 6. This single layout technique can
virtually eliminate high frequency “spike” noise so often
present on switching regulator outputs.
Output ripple voltage appears as a triangular waveform
riding on V
OUT
. Ripple magnitude equals the ripple current
of L2 multiplied by the equivalent series resistance (ESR)
of output capacitor C3. Increasing the inductance of L1
and L2 lowers the ripple current, which leads to lower
output voltage ripple. Decreasing the ESR of C3, by using
ceramic or other low ESR type capacitors, lowers output
ripple voltage. Output ripple voltage can be reduced to
arbitrarily low levels by using large value inductors and
low ESR, high value capacitors.
Figure 5. Switch-On Phase of Inverting Converter. L1 and L2 Current Have Positive dI/dt
Figure 6. Switch-Off Phase of Inverting Converter. L1 and L2 Current Have Negative dI/dt
+
+
L1 L2
C2
–(V
IN
+ V
OUT
)
SW SWX
D1
Q1
1614 F05
C1 C3 R
LOAD
–V
OUT
V
IN
V
CESAT
+
+
L1 L2
C2
V
IN
+ V
OUT
+ V
D
SW SWX
D1
Q1
1614 F06
C1 C3 R
LOAD
–V
OUT
V
IN
V
D
8
LT1614
Transient Response
The inverting architecture of the LT1614 can generate a
very low ripple output voltage. Recently available high
value ceramic capacitors can be used successfully in
LT1614 designs. The addition of a phase lead capacitor,
C
PL
, reduces output perturbations due to load steps when
lower value ceramic capacitors are used and connected in
parallel with feedback resistor R1. Figure 7 shows an
LT1614 inverting converter with resistor loads R
L1
and
R
L2
.
R
L1
is connected across the output, while R
L2
is
switched in externally via a pulse generator. Output volt-
age waveforms are pictured in subsequent figures, illus-
trating the performance of output capacitor type.
Figure 8 shows the output voltage with a 50mA to 200mA
load step, using an AVX TAJ “B” case 33µF tantalum
capacitor at the output. Output perturbation is approxi-
mately 250mV as the load changes from 50mA to 200mA.
Steady-state ripple voltage is 40mV
P–P
, due to L1’s ripple
current and C3’s ESR. Figure 9 pictures the output voltage
and switch pin voltage at 500ns per division. Note the
absence of high frequency spikes at the output. This is
easily repeatable with proper layout, described in the next
section.
OPERATIO
U
In Figure 10, output capacitor C3 is replaced by a ceramic
unit. These large value capacitors have ESR of 2m or less
and result in very low output ripple. A 1nF capacitor, C
PL
,
connected across R1 reduces output perburbation due to
load step. This keeps the output voltage within 5% of
steady-state value. Figure 11 pictures the output and
switch nodes at 500ns per division. Output ripple is about
5mV
P-P
. Again, good layout is essential to achieve this low
noise performance.
Layout
The LT1614 switches current at high speed, mandating
careful attention to layout for best performance.
You will
not get advertised performance with careless layout.
Figure␣ 12
shows recommended component placement. Follow this
closely in your printed circuit layout. The cut ground
copper at D1’s cathode is essential to obtain the low noise
achieved in Figures 10 and 11’s oscillographs. Input
bypass capacitor C1 should be placed close to the LT1614
as shown. The load should connect directly to output
capacitor C2 for best load regulation. You can tie the local
ground into the system ground plane at C3’s ground
terminal.
COMPONENT SELECTION
Inductors
Each of the two inductors used with the LT1614 should
have a saturation current rating (where inductance is
approximately 70% of zero current inductance) of ap-
proximately 0.4A or greater. If the device is used in
“charge pump” mode, where there is only one inductor,
then its rating should be 0.75A or greater. DCR of the
inductors should be 0.4 or less. 22µH inductors are
called out in the applications schematics because these
Murata units are physically small and inexpensive. In-
creasing the inductance will lower ripple current, increas-
ing available output current. A coupled inductor of 33µH,
such as Coiltronics CTX33-2, will provide 290mA at –5V
from a 5V input. Inductance can be reduced if operating
from a supply voltage below 3V. Table 1 lists several
inductors that will work with the LT1614, although this is
not an exhaustive list. There are many magnetics vendors
whose components are suitable.
V
IN
V
IN
5V
–V
OUT
1614 F07
SW
L1
22µH
L2
22µH
D1
GND
LT1614
C1: AVX TAJB226M010
C2: TAIYO YUDEN LMK212BJ105MG
C3: AVX TAJB336M006 OR MURATA (SEE TEXT)
D1: MBR0520
L1, L2: MURATA LQH3C220
C1
C3
C2
1µF
R2
24.9k
R1
69.8k
C
PL
1nF
NFB
SHDN
+
+
R
L1
100
R
L2
33
R
C
C
C
V
C
Figure 7. Switching R
L2
Provides 50mA to 200mA
Load Step for LT1614 5V to –5V Converter
9
LT1614
OPERATIO
U
500µs/DIV 1614 F08
V
OUT
100mV/DIV
AC COUPLED
I
LOAD
200mA
50mA
500ns/DIV
1614 F09
V
OUT
20mV/DIV
AC COUPLED
V
SW
5V/DIV
500µs/DIV
1614 F10
V
OUT
100mV/DIV
AC COUPLED
I
LOAD
200mA
50mA
500ns/DIV
1614 F11
V
OUT
10mV/DIV
AC COUPLED
V
SW
5V/DIV
Figure 8. Load Step Response of LT1614
with 33µF Tantalum Output Capacitor
Figure 9. 33µF “B” Case Tantalum Capacitor Has ESR Resulting
in 40mV
P-P
Voltage Ripple at Output with 200mA Load
Figure 10. Replacing C3 with 22µF Ceramic Capacitor
Lowers Output Voltage Ripple. 1nF Phase-Lead Capacitor
in Parallel with R1 Lowers Transient Excursion
Figure 11. 22µF Ceramic Capacitor at
Output Reduces Output Ripple Voltage
1
2
8
7
3
4
6
5
L1
C2
L2
D1
R
C
R2
C
C
C3
V
IN
GND
SHUTDOWN
1614 F12
C1
+
V
OUT
R1
+
Figure 12. Suggested Component Placement. Note: Cut in Ground Copper at D1’s Cathode

LT1614CS8#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Inv 600kHz Sw Reg
Lifecycle:
New from this manufacturer.
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