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CY26580OI-2

P1-P3P4-P6
CY26580
PacketClock™
Network Applications Clock
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-07536 Rev. *C Revised May 22, 2008
Features
■ Integrated phase-locked loop (PLL)
■ Low-jitter, high-accuracy outputs
■ 3.3V operation
Benefits
■ Internal PLL with precision operation
■ Meets critical timing requirements in complex system designs
■ Enables application compatibility
Table 1. Frequency Table
Part Number Outputs Input Frequency Output Frequencies
CY26580-1 2 125MHz or 25-MHz driven 100 MHz, 133.33 MHz
Table 2. Input Select Options
SEL_25 SEL_CLK Input Type Input Frequency CLK1 CLK2 Unit
X 0 Do not use
0 1 Driven 125 133.33 100 MHz
1 1 Driven 25 133.33 100 MHz
Logic Block Diagram
CLK
OUTPUT
MULTIPLEXER
AND
DIVIDERS
PLL
OSC.
133.33 MHz
Q
P
VCO
VDD
GND
Φ
GND
100 MHz
VDD
SEL_25
SEL_CLK
[+] Feedback
CY26580
Document #: 38-07536 Rev. *C Page 2 of 6
Pin Configuration
Figure 1. CY26580 20-pin SSOP (QSOP)
1
2
3
4
5
6
7
8
14
15
16
17
18
19
20
100 MHz
GND
NC
VDD
NC
SEL_CLK
NC
NC
VDD
9
10
NC
SEL_25
12
11
13
NC
NC
NC
NC
NC
CLK
NC
133 MHz
GND
Table 3. Pin Definition
Pin Name Pin Number Pin Description
NC 1 No Connect
NC 2 No Connect
CLK 3 Reference Input
V
DD
4 Voltage Supply
NC 5 No Connect
GND 6 Ground
NC 7 No Connect
NC 8 No Connect
NC 9 No Connect
133 MHz 10 133.33-MHz Clock Output
SEL_25 11 Reference Frequency Select Input; 0 = 125 MHz, 1 = 25 MHz, weak internal pull up
NC 12 No Connect
NC 13 No Connect
GND 14 Ground
NC 15 No Connect
V
DD
16 Voltage Supply
100 MHz 17 100-MHz Clock Output
NC 18 No Connect
SEL_CLK 19 Reference Select Input; Set to 1 = Driven, weak internal pull up
NC 20 No Connect
[+] Feedback
CY26580
Document #: 38-07536 Rev. *C Page 3 of 6
Absolute Maximum Conditions
[1]
Supply Voltage (V
DD
)........................................–0.5 to +7.0V
DC Input Voltage ....................................... –0.5V to V
DD
+0.5
Storage Temperature (Non-condensing) .... –55°C to +125°C
Junction Temperature................................ –40°C to +125°C
Data Retention at Tj = 125°C ................................> 10 years
Package Power Dissipation......................................350 mW
ESD (Human Body Model) MIL-STD-883.................... 2000V
Figure 2. Test and Measurement Setup
Notes
1. Above which the useful life may be impaired. For user guidelines, not tested.
2. Guaranteed by characterization, not 100% tested.
Recommended Operating Conditions
Parameter Description Min Typ. Max Unit
V
DD
Supply Voltage 3.14 3.3 3.47 V
T
A
, I-grade Ambient Temperature, Industrial –40 – 85 °C
C
LOAD
Max. Load Capacitance – – 15 pF
f
REF
Reference Frequency – 125, 25 – MHz
DC Electrical Specifications
Parameter
[2]
Description Conditions Min Typ. Max Unit
I
OH
Output High Current V
OH
= V
DD
– 0.5, V
DD
= 3.3V 12 24 – mA
I
OL
Output Low Current V
OL
= 0.5, V
DD
= 3.3V 12 24 – mA
I
IH
Input High Current V
IH
= V
DD
–510μA
I
IL
Input Low Current V
IL
= 0V – – 50 μA
V
IH
Input High Voltage CMOS levels, 70% of V
DD
0.7 – – V
DD
V
IL
Input Low Voltage CMOS levels, 30% of V
DD
––0.3V
DD
I
DD
Supply Current V
DD
Current, no load – 35 50 mA
R
UP
Pull up resistor on Inputs V
DD
= 3.14 to 3.47V, measured V
IN
= 0V – 100 150 kΩ
AC Electrical Specifications
Parameter
[2]
Description Conditions Min Typ. Max Unit
F
error
Frequency Error All clocks 0 ppm
DC Output Duty Cycle Duty Cycle is defined in Figure 3, 50% of V
DD
45 50 55 %
ER Rising Edge Rate Output Clock Edge Rate, Measured from 20% to
80% of V
DD
, C
LOAD
= 15 pF. See Figure 4.
0.8 1.4 2 V/ns
EF Falling Edge Rate Output Clock Edge Rate, Measured from 80% to
20% of V
DD
, C
LOAD
= 15 pF. See Figure 4.
0.8 1.4 2 V/ns
t
9
Clock Jitter CLK1, CLK2 Peak-Peak period jitter – 100 – ps
t
10
PLL Lock Time – – 3 ms
0.1
μ
F
V
DDs
Outputs
C
LOAD
GND
DUT
[+] Feedback
P1-P3P4-P6

CY26580OI-2

Mfr. #:
Buy CY26580OI-2
Manufacturer:
Cypress Semiconductor
Description:
Phase Locked Loops - PLL PacketClockClk
Lifecycle:
New from this manufacturer.
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