Characteristics P011xx
4/9
Figure 5. Relative variation of gate trigger,
holding and latching current versus
junction temperature
Figure 6. Relative variation of holding
current versus gate-cathode
resistance (typical values)
-40 -20 0 20 40 60 80 100 120 14
0
1
2
3
4
5
6
T (°C)
j
I,I,I[T] /
GT H L j
I ,I ,I [T =25°C]
GT H L j
I
GT
I
H
& I
R = 1k
L
GK
Ω
typical values
1E-2 1E-1 1E+0 1E+1
0
2
4
6
8
10
12
14
16
18
20
R(k)
GK
Ω
I [R ] / I [ =1k ]
HGK H
ΩR
GK
T
j
= 25°C
Figure 7. Relative variation of dV/dt immunity
versus gate-cathode resistance
(typical values).
Figure 8. Relative variation of dV/dt immunity
versus gate-cathode capacitance
(typical values)
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
0.1
1.0
10.0
R(k)
GK
Ω
dV/dt[R ] / dV/dt[ =1k ]
GK
ΩR
GK
T
j
= 125°C
V = 0.67 x V
D DRM
01234567
0
2
4
6
8
10
C (nF)
GK
dV/dt[C ] / dV/dt[ =1k ]
GK
ΩR
GK
T
V = 0.67 x V
= 125°C
R = 1k
D DRM
GK
j
Ω
Figure 9. Surge peak on-state current versus
number of cycles
Figure 10. Non-repetitive surge peak on-state
current and corresponding value
of I²t
I (A)
TSM
1 10 100 1000
0
1
2
3
4
5
6
7
8
Number of cycles
Non repetitive
T initial=25°C
j
Repetitive
T =25°C
amb
t =10ms
p
One cycle
I (A), I t (A s)
TSM
22
100.0
10.0
1.0
0.1
0.01
0.10
1.00
10.00
T initial = 25°C
j
I t
2
I
TSM
t (ms)
p
sinusoidal pulse with
width t < 10ms
p
