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LTC3805MPMSE-5#TRPBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
LTC3805-5
10
38055fe
OPERATION
First, consider operation without overcurrent protection.
For some maximum converter output current, the voltage
on the I
TH
pin rises to and is clamped at approximately 1.9V.
This corresponds to a 100mV limit on the voltage at the
I
SENSE
pin. As the output current is further increased, the
duty cycle is reduced as the output voltage sags. However,
the peak current in the external MOSFET is limited by the
100mV threshold at the I
SENSE
pin.
As the output current is increased further, eventually,
the duty cycle is reduced to the 6% minimum. Since the
external MOSFET is always turned on for this minimum
amount of time, the current comparator no longer limits
the current through the external MOSFET based on the
100mV threshold. If the output current continues to in-
crease, the current through the MOSFET could rise to a
level that would damage the converter.
To prevent damage, the overcurrent pin, OC, is also
connected to the current sense resistor, and a fault is
triggered if the voltage on the OC pin exceeds 100mV. To
protect itself, the converter stops operating as described
in the next section. External resistors can be used to ad-
just the overcurrent threshold to voltages higher or lower
than 100mV as described in the Applications Information
section.
Soft-Start and Fault Timeout Operation
The soft-start and fault timeout of the LTC3805-5 uses either
a fixed internal timer or an external timer programmed
by a capacitor from the SSFLT pin to GND. The internal
soft-start and fault timeout times are minimums and can
be increased by placing a capacitor from the SSFLT pin
to GND. Operation is shown in Figure 1.
Leave the SSFLT pin open to use the internal soft-start and
fault timeout. The internal soft-start is complete in about
1.8ms. In the event of an overcurrent as detected by the
OC pin exceeding 100mV, the LTC3805-5 shuts down and
an internal timing circuit waits for a fault timeout of about
4.25ms and then restarts the converter.
Add a capacitor C
SS
from the SSFLT pin to GND to increase
both the soft-start time and the time for fault timeout. Dur-
ing soft-start, C
SS
is charged with a 6µA current. When the
LTC3805-5 comes out of shutdown, the LTC3805-5 quickly
charges C
SS
to about 0.7V at which point GATE begins
switching. From that point, GATE continues switching with
increasing duty cycle until the SSFLT pin reaches about
2.25V at which point soft-start is over and closed-loop
regulation begins. The voltage on the SSFLT pin addition-
ally further charges to about 4.75V.
C
SS
also performs the timeout function in the event of a
fault. After a fault, C
SS
is slowly discharged from about
4.75V to about 0.7V by a 2µA current. When the voltage
on the SSFLT pin reaches 0.7V the converter attempts to
restart. More detail on programming the external soft-start
fault timeout is described in the Applications Information
section.
Powering the LTC3805-5
A built-in shunt regulator from the V
CC
pin to GND limits
the voltage on the V
CC
pin to approximately 9.5V as long
as the shunt regulator is not forced to sink more than
25mA. The shunt regulator is always active, even when
the LTC3805-5 is in shutdown, since it serves the vital
function of protecting the V
CC
pin from overvoltage. The
shunt regulator permits the use of a wide variety of pow-
ering schemes for the LTC3805-5 even from high voltage
sources that exceed the LTC3805-5’s absolute maximum
ratings. Further details on powering schemes are described
in the Applications Information section.
Adjustable Slope Compensation
The LTC3805-5 injects a 10µA peak current ramp out of
its I
SENSE
pin which can be used, in conjunction with an
external resistor, for slope compensation in designs that
require it. This current ramp is approximately linear and
begins at zero current at 6% duty cycle, reaching peak
current at 80% duty cycle. Additional details are provided
in the Applications Information section.
LTC3805-5
11
38055fe
APPLICATIONS INFORMATION
Many LTC3805-5 application circuits can be derived from
the topologies shown on the first page or in the Typical
Applications section of this data sheet.
The LTC3805-5 itself imposes no limits on allowed input
voltage V
IN
or output voltage V
OUT
. These are all determined
by the ratings of the external power components. In Figure 8,
the factors are: Q1 maximum drain-source voltage (B
VDSS
),
on-resistance (R
DS(ON)
) and maximum drain current, T1
saturation flux level and winding insulation breakdown
voltages, C
IN
and C
OUT
maximum working voltage, equiva-
lent series resistance (ESR), and maximum ripple current
ratings, and D1 and R
SENSE
power ratings.
V
CC
Bias Power
The V
CC
pin must be bypassed to the GND pin with a
minimum 1µF ceramic or tantalum capacitor located im-
mediately adjacent to the two pins. Proper supply bypassing
is necessary to supply the high transient currents required
by the MOSFET gate driver.
For maximum flexibility, the LTC3805-5 is designed so
that it can be operated from voltages well beyond the
LTC3805-5’s absolute maximum ratings. Figure 2 shows
the simplest case, in which the LTC3805-5 is powered
with a resistor R
VCC
connected between the input voltage
and V
CC
. The built-in shunt regulator limits the voltage on
the V
CC
pin to around 9.5V as long as the internal shunt
regulator is not forced to sink more than 25mA. This pow-
ering scheme has the drawback that the power loss in the
resistor reduces converter efficiency and the 25mA shunt
regulator maximum may limit the maximum-to-minimum
range of input voltage.
The typical application circuit in Figure 9 shows a different
flyback converter bias power strategy for a case in which
neither the input or output voltage is suitable for providing
bias power to the LTC3805-5. A small NPN preregulator
transistor and a Zener diode are used to accelerate the
rise of V
CC
and reduce the value of the V
CC
bias capacitor.
The flyback transformer has an additional bias winding to
provide bias power. Note that this topology is very power-
ful because, by appropriate choice of transformer turns
ratio, the output voltage can be chosen without regard to
the value of the input voltage or the V
CC
bias power for
the LTC3805-5. The number of turns in the bias winding
is chosen according to
N
BIAS
= N
SEC
V
CC
+ V
D2
V
OUT
+ V
D1
where N
BIAS
is the number of turns in the bias winding,
N
SEC
is the number of turns in the secondary winding,
V
CC
is the desired voltage to power the LTC3805-5, V
OUT
is the converter output voltage, V
D1
is the forward voltage
drop of D1 and V
D2
is the forward voltage drop of D2.
Note that since V
OUT
is regulated by the converter control
loop, V
CC
is also regulated although not as precisely. If an
“off-the-shelf” transformer with excessive bias windings
is used, the resistor, R
BIAS
in Figure 9, can be added to
limit the current.
Transformer Design Considerations
Transformer specification and design is perhaps the most
critical part of applying the LTC3805-5 successfully. In
addition to the usual list of caveats dealing with high fre-
quency power transformer design, the following should
prove useful.
Turns Ratios
Due to the use of the external feedback resistor divider
ratio to set output voltage, the user has relative freedom
in selecting transformer turns ratio to suit a given ap-
plication. Simple ratios of small integers, e.g., 1:1, 2:1,
3:2, etc. can be employed which yield more freedom in
setting total turns and transformer inductance. Simple
integer turns ratios also facilitate the use of “off-the-shelf”
configurable transformers. Turns ratio can be chosen on
Figure 2. Powering the LTC3805-5 via the
Internal Shunt Regulator
LTC3805-5
V
CC
R
VCC
C
VCC
38055 F02
V
IN
GND
LTC3805-5
12
38055fe
APPLICATIONS INFORMATION
the basis of desired duty cycle. However, remember that
the input supply voltage plus the secondary-to-primary
referred version of the flyback pulse (including leakage
spike) must not exceed the allowed external MOSFET
breakdown rating.
Leakage Inductance
Transformer leakage inductance (on either the primary
or secondary) causes a voltage spike to occur after the
turn off of MOSFET (Q1) in Figure 8. This is increasingly
prominent at higher load currents, where more stored
energy must be dissipated. In some cases an RC “snubber”
circuit will be required to avoid overvoltage breakdown at
the MOSFET’s drain node. Application Note 19 is a good
reference on snubber design. A bifilar or similar winding
technique is a good way to minimize troublesome leak-
age inductances. However, remember that this will limit
the primary-to-secondary breakdown voltage, so bifilar
winding is not always practical.
Setting Undervoltage and Hysteresis on V
IN
The RUN pin is connected to a resistive voltage divider
connected to V
IN
as shown in Figure 3. The voltage thresh-
old for the RUN pin is V
RUNON
rising and V
RUNOFF
falling.
Note that V
RUNON
– V
RUNOFF
= 35mV of built-in voltage
hysteresis that helps eliminate false trips.
To introduce further user-programmable hysteresis, the
LTC3805-5 sources 5µA out of the RUN pin when operation
of LTC3805-5 is enabled. As a result, the falling threshold
for the RUN pin also depends on the value of R1 and can
be programmed by the user. The falling threshold for V
IN
is therefore
V
IN(RUN,FALLING)
= V
RUNOFF
•
R1+ R2
− R1• 5µA
where R1(5µA) is the additional hysteresis introduced
by the 5µA current sourced by the RUN pin. When in
shutdown, the RUN pin does not source the 5µA current
and the rising threshold for V
IN
is simply
V
IN(RUN,RISING)
= V
RUNON
•
R1+ R2
R2
Note that for some applications the RUN pin can be con-
nected to V
CC
in which case the V
CC
thresholds, V
TURNON
and V
TURNOFF
, control operation.
External Run/Stop Control
To implement external run control, place a small N-channel
MOSFET from the RUN pin to GND as shown in Figure 3.
Drive the gate of this MOSFET high to pull the RUN pin
to ground and prevent converter operation.
Selecting Feedback Resistor Divider Values
The regulated output voltage is determined by the resistor
divider across V
OUT
(R3 and R4 in Figure 8). The ratio
of R4 to R3 needed to produce a desired V
OUT
can be
calculated:
R3=
V
OUT
− 0.8V
0.8V
R4
Choose resistance values for R3 and R4 to be as large as
possible in order to minimize any efficiency loss due to the
static current drawn from V
OUT
, but just small enough so
that when V
OUT
is in regulation the input current to the V
FB
pin is less than 1% of the current through R3 and R4. A
good rule of thumb is to choose R4 to be less than 80k.
Figure 3. Setting RUN Pin Voltage and Run/Stop Control
LTC3805-5
RUN
RUN/STOP
CONTROL
(OPTIONAL)
R1
R2
GND
38055 F03
V
IN
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LTC3805MPMSE-5#TRPBF

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Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Selectable Frequency Current Mode Flyback DC/DC Controller
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