2001 Feb 02 13
NXP Semiconductors Product specification
Low-cost stereo filter DAC UDA1330ATS
DC CHARACTERISTICS
V
DDD
=V
DDA
=5.0V; T
amb
=25°C; R
L
=5kΩ; all voltages referenced to ground (pins V
SSA
and V
SSD
); unless
otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Supplies
V
DDA
DAC analog supply voltage note 1 2.7 5.0 5.5 V
V
DDD
digital supply voltage note 1 2.7 5.0 5.5 V
I
DDA
DAC analog supply current V
DDA
=5.0V
operating 9.5 mA
power-down 400 −μA
V
DDA
=3.3V
operating 7.0 mA
power-down 250 −μA
I
DDD
digital supply current V
DDD
=5.0V 5.5 mA
V
DDD
=3.3V 3.0 mA
Power dissipation
P power dissipation playback mode
V
DDA
=V
DDD
=5.0V 75 mW
V
DDA
=V
DDD
=3.3V 33 mW
Digital inputs: pins BCK, WS, DATAI, SYSCLK, APPL0, APPL1, APPL2 and APPL3 (note 2)
V
IH
HIGH-level input voltage V
DDD
= 5.0 V 2.2 −−V
V
DDD
= 3.3 V 1.45 −−V
V
IL
LOW-level input voltage V
DDD
=5.0V −−0.8 V
V
DDD
=3.3V −−0.5 V
I
LI
input leakage current −−1 μA
C
i
input capacitance −−10 pF
Three-level input: APPSEL
V
IH
HIGH-level input voltage 0.9V
DDD
V
DDD
+0.5 V
V
IM
MIDDLE-level input
voltage
0.4V
DDD
0.6V
DDD
V
V
IL
LOW-level input voltage 0.5 +0.1V
DDD
V
2001 Feb 02 14
NXP Semiconductors Product specification
Low-cost stereo filter DAC UDA1330ATS
Notes
1. All supply connections must be made to the same external power supply unit.
2. The digital input pads are TTL compatible at 5 V, but the pads are not 5 V tolerant in the voltage range between
2.7 and 4.5 V.
3. When the DAC drives a capacitive load above 50 pF, a series resistance of 100 Ω must be used to prevent
oscillations in the output operational amplifier.
AC CHARACTERISTICS
f
i
= 1 kHz; T
amb
=25°C; R
L
=5kΩ; all voltages referenced to ground (pins V
SSA
and V
SSD
); unless otherwise specified.
DAC
V
ref(DAC)
reference voltage with respect to V
SSA
0.45V
DDA
0.5V
DDA
0.55V
DDA
V
I
o(max)
maximum output current (THD + N)/S < 0.1%;
R
L
=5kΩ
0.36 mA
R
o
output resistance 0.15 2.0 Ω
R
L
load resistance 3 −−kΩ
C
L
load capacitance note 3 −−50 pF
SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT
Digital-to-analog converter (V
DDA
=V
DDD
=5.0V)
V
o(rms)
output voltage (RMS value) 1.45 V
ΔV
o
unbalance between channels 0.1 dB
(THD + N)/S total harmonic distortion-plus-noise to
signal ratio
at 0 dB 90 85 dB
at 60 dB; A-weighted 40 35 dB
S/N signal-to-noise ratio code = 0; A-weighted 100 95 dB
α
cs
channel separation 100 dB
Digital-to-analog converter (V
DDA
=V
DDD
=3.3V)
V
o(rms)
output voltage (RMS value) 1.0 V
ΔV
o
unbalance between channels 0.1 dB
(THD + N)/S total harmonic distortion-plus-noise to
signal ratio
at 0 dB 85 dB
at 60 dB; A-weighted 38 dB
S/N signal-to-noise ratio code = 0; A-weighted 100 dB
α
cs
channel separation 100 dB
PSRR power supply ripple rejection f
ripple
=1kHz;
V
ripple
= 100 mV (p-p)
60 dB
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
2001 Feb 02 15
NXP Semiconductors Product specification
Low-cost stereo filter DAC UDA1330ATS
TIMING
V
DDD
=V
DDA
= 4.5 to 5.5 V; T
amb
= 40 to +85 °C; R
L
=5kΩ; all voltages referenced to ground (pins V
SSA
and V
SSD
);
unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
System clock (see Fig.7)
T
sys
system clock cycle time f
sys
= 256f
s
71 88 488 ns
f
sys
= 384f
s
47 59 325 ns
f
sys
= 512f
s
36 44 244 ns
t
CWL
LOW-level system clock pulse width f
sys
< 19.2 MHz 0.3T
sys
0.7T
sys
ns
f
sys
19.2 MHz 0.4T
sys
0.6T
sys
ns
t
CWH
HIGH-level system clock pulse width f
sys
< 19.2 MHz 0.3T
sys
0.7T
sys
ns
f
sys
19.2 MHz 0.4T
sys
0.6T
sys
ns
Digital interface (see Fig.8)
T
cy(BCK)
bit clock cycle time 300 −−ns
t
BCKH
bit clock HIGH time 100 −−ns
t
BCKL
bit clock LOW time 100 −−ns
t
r
rise time −−20 ns
t
f
fall time −−20 ns
t
su(DATAI)
data input set-up time 20 −−ns
t
h(DATAI)
data input hold time 0 −−ns
t
su(WS)
word select set-up time 20 −−ns
t
h(WS)
word select hold time 10 −−ns
Control interface L3 mode (see Figs 4 and 5)
T
cy(CLK)L3
L3CLOCK cycle time 500 −−ns
t
CLK(L3)H
L3CLOCK HIGH time 250 −−ns
t
CLK(L3)L
L3CLOCK LOW time 250 −−ns
t
su(L3)A
L3MODE set-up time for address mode 190 −−ns
t
h(L3)A
L3MODE hold time for address mode 190 −−ns
t
su(L3)D
L3MODE set-up time for data transfer
mode
190 −−ns
t
h(L3)D
L3MODE hold time for data transfer
mode
190 −−ns
t
su(L3)DA
L3DATA set-up time for data transfer and
address mode
190 −−ns
t
h(L3)DA
L3DATA hold time for data transfer and
address mode
30 −−ns
t
stp(L3)
L3MODE stop time for data transfer
mode
190 −−ns

UDA1330ATS/N2,118

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
Audio D/A Converter ICs 5V LOWCOST DAC
Lifecycle:
New from this manufacturer.
Delivery:
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