RT8010B
10
DS8010B-04 March 2011www.richtek.com
In continuous mode, the average output current flowing
through inductor L is “chopped” between the main switch
and the synchronous switch. Thus, the series resistance
looking into the LX pin is a function of both top and bottom
MOSFET R
DS(ON)
and the duty cycle (DC) as follows :
R
SW
= R
DS(ON)TOP
x DC + R
DS(ON)BOT
x (1−DC)
The R
DS(ON)
for both the top and bottom MOSFETs can be
obtained from the Typical Performance Characteristics
curves. Thus, to obtain I
2
R losses, simply add R
SW
to R
L
and multiply the result by the square of the average output
current.
Other losses including C
IN
and C
OUT
ESR dissipative
losses and inductor core losses generally account for less
than 2% of the total loss.
Thermal Considerations
For continuous operation, do not exceed the maximum
operation junction temperature 125°C. The maximum
power dissipation depends on the thermal resistance of
IC package, PCB layout, the rate of surroundings airflow
and temperature difference between junction to ambient.
The maximum power dissipation can be calculated by
following formula :
P
D(MAX)
= ( T
J(MAX)
− T
A
) / θ
JA
Where T
J(MAX)
is the maximum operation junction
temperature 125°C, T
A
is the ambient temperature and the
θ
JA
is the junction to ambient thermal resistance.
For recommended operating conditions specification of
RT8010B, where T
J(MAX)
is the maximum junction
temperature of the die (125°C) and T
A
is the maximum
ambient temperature. The junction to ambient thermal
resistance θ
JA
is layout dependent. For WDFN-8L 2x2
packages, the thermal resistance θ
JA
is 165°C/W on the
standard JEDEC 51-7 four layers thermal test board. The
maximum power dissipation at T
A
= 25°C can be calculated
by following formula :
P
D(MAX)
= ( 125°C − 25°C ) / (165°C/W) = 0.606W for
WDFN-8L 2x2 packages
The maximum power dissipation depends on operating
ambient temperature for fixed T
J(MAX)
and thermal
resistance θ
JA
.
Checking Transient Response
The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V
OUT
immediately shifts by an amount
equal to ΔI
LOAD
(ESR), where ESR is the effective series
resistance of C
OUT
. ΔI
LOAD
also begins to charge or
discharge C
OUT
generating a feedback error signal used
by the regulator to return V
OUT
to its steady-state value.
During this recovery time, V
OUT
can be monitored for
overshoot or ringing that would indicate a stability problem.
Layout Considerations
Follow the PCB layout guidelines for optimal performance
of RT8010B.
` Put the input capacitor as close as possible to the device
pins (VIN and GND).
` LX node is with high frequency voltage swing and should
be kept small area. Keep analog components away from
LX node to prevent stray capacitive noise pick-up.
` Connect feedback network behind the output capacitors.
Keep the loop area small. Place the feedback
components near the RT8010B.
` Connect all analog grounds to a command node and
then connect the command node to the power ground
behind the output capacitors.
Figure 5. Derating Curves for RT8010B Package
For RT8010B packages, the Figure 5 of derating curves
allows the designer to see the effect of rising ambient
temperature on the maximum power allowed.
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0 25 50 75 100 125
Ambient Temperature (°C)
Maximum Power Dissipation (W)
Four Layers PCB
(°C)
WDFN-8L 2x2
