12 2006 Semtech Corp. www.semtech.com
SC4806
POWER MANAGEMENT
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Careful attention to layout requirements are necessary for
successful implementation of the SC4806 PWM control-
ler.
High current switching is present in the application and
their effect on ground plane voltage differentials must be
understood and minimized.
1) The high power parts of the circuit should be laid out
first. A ground plane should be used, the number and po-
sition of ground plane interruptions should be such as to
not unnecessarily compromise ground plane integrity. Iso-
lated or semi-isolated areas of the ground plane may be
deliberately introduced to constrain ground currents to
particular areas, such as the input capacitor and FET
ground.
2) In the loop formed by the Input Capacitor(s) (Cin), the
FET must be kept as small as possible. This loop contains
all the high current, fast transition switching. Connections
should be as wide and as short as possible to minimize
loop inductance. Minimizing this loop area will a) reduce
EMI, b) lower ground injection currents, resulting in electri-
cally “cleaner” grounds for the rest of the system and c)
minimize source ringing, resulting in more reliable gate
switching signals.
3) The connection between FETs and the Transformer
should be a wide trace or copper region. It should be as
short as practical. Since this connection has fast voltage
transitions, keeping this connection short will minimize
EMI.
4) The Output Capacitor(s) (Cout) should be located as
close to the load as possible. Fast transient load cur-
rents are supplied by Cout only, and connections between
Cout and the load must be short, wide copper areas to
minimize inductance and resistance.
5) A SC4806 is best placed over a quiet ground plane
area. Avoid pulse currents in the Cin FET loop flowing in
this area. GND should be returned to the ground plane
close to the package and close to the ground side of
(one of) the VCC supply capacitor(s). Under no circum-
stances should GND be returned to a ground inside the
Cin, Q1, Q2 loop. Avoid making a star connection be-
Application Information (Cont.)
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During start up of the converter, the discharged output
capacitor and the load current have large supply current
requirements. To avoid this a soft start scheme is usu-
ally implemented where the duty cycle of the regulator is
gradually increased from 0% until the soft start duration
is elapsed.
SC4806 has soft start circuit with an external capacitor
that limits the duty cycle for a duration approximated by
the formula below. Also the soft start circuitry is acti-
vated if an over current condition occurs. After an over
current condition, OUTA and OUTB are disabled and kept
low. After the delay, the OUTA and OUTB are enabled while
the soft start limits the duty cycle. If the over current
condition persists, the soft start cycle repeats indefinitely.
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Initially during the power up, the SC4806 is in under volt-
age lock out condition. As the Vcc supply exceeds the
UVLO limit of the SC4806, the internal reference, oscil-
lator, and logic circuitry are powered up.
The OUTA and OUTB drivers are not enabled until the line
under voltage lock out limit is reached. At that point, once
the FB pin is above 1.5V, soft start circuitry starts the
output drivers, and gradually increases the duty cycle from
0%.
As the output voltage starts to increase, the error signal
from the error amplifier starts to decrease. If isolation is
required, the error amplifier output can drive the LED of
the opto isolator. The output of the opto is connected in
a common emitter configuration with a pull-up resistor
to a reference voltage connected to the FB pin of the
SC4806. The voltage level at the FB pin provides the
duty cycle necessary to achieve regulation.
If an over current condition occurs, the outputs are dis-
abled and after a soft start delay time of about 100µs,
the soft-start sequence mentioned above is repeated.
