ISL6729
5
FN9152.3
December 21, 2016
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Pin Descriptions
CLK - This is the oscillator timing control pin. The operational
frequency and maximum duty cycle are set by applying a 5V
amplitude clock signal to CLK. The logic high duration defines
the maximum ON time for the output. A maximum clock rate
up to 2.0MHz is possible.
COMP - COMP is the input to the PWM comparator and is
typically controlled through an external error amplifier.
CS - This is the current sense input to the PWM comparator.
The range of the input signal is nominally 0 to 1.0V and has an
internal offset of 100mV.
GND - GND is the power and small signal reference ground for
all functions.
OUT - This is the drive output to the power switching device. It is
a high current output capable of driving the gate of a power
MOSFET with peak currents of 1.0A. This GATE output is
actively held low when V
DD
is below the UVLO threshold.
VDD - VDD is the 5V power connection for the IC. The IC will
operate from 4.75V to 5.25V. However, the accuracy of the
voltage clamp on the COMP signal, which determines the
overcurrent threshold, is dependent on the accuracy of VDD. A
tight tolerance on VDD will result in a tight overcurrent
threshold.
The total supply current will depend on the load applied to OUT.
Total I
DD
current is the sum of the operating current and the
average output current. Knowing the operating frequency, f,
and the MOSFET gate charge, Qg, the average output current
can be calculated from:
To optimize noise immunity, bypass VDD to GND with a
ceramic capacitor as close to the VDD and GND pins as
possible.
Ground Plane Requirements
Careful layout is essential for satisfactory operation of the
device. A good ground plane must be employed. A unique
section of the ground plane must be designated for high di/dt
currents associated with the output stage. VDD should be
bypassed directly to GND with good high frequency capacitors.
Applications Information
Microcontrollers are becoming more popular for monitoring and
supervisory functions in power converters due to their flexibility,
capability, and declining prices. Many applications would like to
take advantage of this flexibility and use them to perform the
control loop function as well. There are many examples of
voltage mode control using digital signal processing techniques.
However, microcontrollers available today do not have the
execution speed required for peak current mode control at the
operational frequencies of modern switch-mode power supplies.
As such, they are unable to detect the peak current and
terminate the switching cycle within the few nanosecond
window required. The ISL6729 provides the analog circuitry
required to perform peak current control, but delegates the
oscillator function to the microcontroller. This arrangement
allows the microcontroller to control soft-start, maximum duty
cycle, and operational frequency of the power converter, as well
as performing the traditional overhead functions such as fault
monitoring and system interface.
Application of the ISL6729 is similar to the ISL684x family of
PWM converters except that the input bias voltage has been
changed to 5V and the oscillator, reference, and error amplifier
functions have been removed. An external digital clock signal,
such as the PWM output of a microcontroller, must be supplied
to control the frequency and maximum duty cycle. The
frequency of the applied clock signal and the frequency of
operation of the PWM are identical. The duty cycle of the clock
is the maximum duty cycle of the PWM. Soft-start may be
accomplished by incrementing the duty cycle of the applied
clock signal from zero to the maximum desired value in a time
frame appropriate for the application.
Figure 2 on page 3
illustrates how the ISL6729 may be used for
an interleaved power converter. In this example, three clock
signals of equal duty cycle, but phased 120° apart, are applied
to separate power stages. Each phase shares a common voltage
feedback signal, but uses separate current feedback signals
from each power stage for regulation. Excellent current sharing
behavior is assured since each phase must produce the same
peak current. Accuracy is determined by the variation of the
output inductor value and the feedback components.
Multiple output power supplies can be created in a similar
fashion. Only one clock signal is required if in-phase operation
is desired. Each stage may be independently controlled using
separate voltage and current feedback loops.
PWM
Maximum Duty Cycle -99-%
Minimum Duty Cycle --0%
NOTES:
6. Specifications at -40°C are established by design, not production tested.
7. This i s the V
DD
current consumed when the device is active but not switching. Does not include gate drive current.
8. Established by design, not 100% tested in production.
Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to Figure 1 on page 2 and Figure 2 on
page 3. V
DD
= 5V, CLK = 50kHz, T
A
= -40 to +105°C (Note 6), Typical values are at T
A
= +25°C (Continued)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
