IS31SE5104
Integrated Silicon Solution, Inc. – www.issi.com 6
Rev. C, 08/05/2015
DETAILED DESCRIPTION
I2C INTERFACE
The IS31SE5104 uses a serial bus, which conforms to
the I2C protocol, to control the chip’s functions with two
wires: SCL and SDA. The IS31SE5104 has a 7-bit slave
address (A7:A1), followed by the R/W bit, A0. Set A0 to
“0” for a write command and set A0 to “1” for a read
command. The value of bits A1 and A2 are decided by
the connection of the AD pin.
The complete slave address is:
Table 1 Slave Address
Bit A7:A3 A2:A1 A0
Value 10001
AD
1/0
AD connected to GND, AD = 00;
AD connected to VCC, AD = 11;
AD connected to SCL, AD = 01;
AD connected to SDA, AD = 10;
The SCL line is uni-directional. The SDA line is
bi-directional (open-collector) with a pull-up resistor
(typically 4.7k). The maximum clock frequency
specified by the I2C standard is 400kHz. In this
discussion, the master is the microcontroller and the
slave is the IS31SE5104.
The timing diagram for the I2C is shown in Figure 2.
The SDA is latched in on the stable high level of the
SCL. When there is no interface activity, the SDA line
should be held high.
The “START” signal is generated by lowering the SDA
signal while the SCL signal is high. The start signal will
alert all devices attached to the I2C bus to check the
incoming address against their own chip address.
The 8-bit chip address is sent next, most significant bit
first. Each address bit must be stable while the SCL
level is high.
After the last bit of the chip address is sent, the master
checks for the IS31SE5104’s acknowledge. The
master releases the SDA line high (through a pull-up
resistor). Then the master sends an SCL pulse. If the
IS31SE5104 has received the address correctly, then it
holds the SDA line low during the SCL pulse. If the SDA
line is not low, then the master should send a “STOP”
signal (discussed later) and abort the transfer.
Following acknowledge of IS31SE5104, the register
address byte is sent, most significant bit first.
IS31SE5104 must generate another acknowledge
indicating that the register address has been received.
Then 8-bit of data byte are sent next, most significant
bit first. Each data bit should be valid while the SCL
level is stable high. After the data byte is sent, the
IS31SE5104 must generate another acknowledge to
indicate that the data was received.
The “STOP” signal ends the transfer. To signal “STOP”,
the SDA signal goes high while the SCL signal is high.
READING PORT REGISTERS
To read the device data, the bus master must first send
the IS31SE5104 address with the R/W
____
bit set to “0”,
followed by the command byte, which determines
which register is accessed. After a restart, the bus
master must then send the IS31SE5104 address with
the R/W
____
bit set to “1”. Data from the register defined
by the command byte is then sent from the
IS31SE5104 to the master (Figure 5).
Figure 2 Interface timing
Figure 3 Bit transfer
