11©2017 Integrated Device Technology, Inc. Revision 7, January 9, 2017
82P33814 Datasheet
48 CLKE/I2C_AD1
I
pull-down
CMOS
CLKE: SCLK Active Edge Selection
In Serial mode, this pin is an input, it selects the active edge of SCLK to update the SDO:
High - The falling edge;
Low - The rising edge.
I2C_AD1: Device Address Bit 1
In I2C mode, I2C_AD[2:0] pins are the address bus of the microprocessor interface.
49 CS/I2C_AD0
I
pull-up
CMOS
CS: Chip Selection
In Serial modes, this pin is an input.A transition from high to low must occur on this pin for
each read or write operation and this pin should remain low until the operation is over.
I2C_AD0: Device Address Bit 0
In I2C mode, I2C_AD[2:0] pins are the address bus of the microprocessor interface.
50 SCLK/I2C_SCL I CMOS
SCLK: Shift Clock
In Serial mode, a shift clock is input on this pin.
Data on SDI is sampled by the device on the rising edge of SCLK. Data on SDO is updated
on the active edge of SCLK. The active edge is determined by the CLKE.
I2C_SCL: Serial Clock Line
In I2C mode, the serial clock is input on this pin.
51
SDO/I2C_SDA/
UART_TX
I/O
CMOS
Open Drain
SDO: Serial Data Output
In Serial mode, this pin is used as the serial data output. Data on this pin is serially clocked
out of the device on the active edge of SCLK.
I2C_SDA: Serial Data Input/Output
In I2C mode, this pin is used as the input/output for the serial data.
UART_TX:
In UART mode, this pin is used as the transmit data (UART Transmit)
JTAG (per IEEE 1149.1)
14 TMS
I
pull-up
CMOS
TMS: JTAG Test Mode Select
The signal on this pin controls the JTAG test performance and is sampled on the rising edge
of TCK.
15 TRSTB
I
pull-up
CMOS
TRSTB: JTAG Test Reset (Active Low)
A low signal on this pin resets the JTAG test port.
This pin should be connected to ground when JTAG is not used.
16 TCK
I
pull-down
CMOS
TCK: JTAG Test Clock
The clock for the JTAG test is input on this pin. TDI and TMS are sampled on the rising edge
of TCK and TDO is updated on the falling edge of TCK.
If TCK is idle at a low level, all stored-state devices contained in the test logic will indefinitely
retain their state.
17 TDI
I
pull-up
CMOS
TDI: JTAG Test Data Input
The test data are input on this pin. They are clocked into the device on the rising edge of
TCK.
18 TDO
O
tri-state
CMOS
TDO: JTAG Test Data Output
The test data are output on this pin. They are clocked out of the device on the falling edge of
TCK.
TDO pin outputs a high impedance signal except during the process of data scanning.
Power & Ground
2, 3, 4, 5, 10 11, 12 VDDA Power -
VDDA: Analog Core Power - +3.3V DC nominal
20, 24, 69, 72 VDDAO Power
VDDAO: Analog Output Power - +3.3V DC nominal
27, 29, 64, 66 VDDDO Power
VDDDO: Digital Output Power - +3.3V DC nominal
Table 1: Pin Description (Continued)
Pin No. Name I/O Type
Description
