LT3592
19
3592fc
APPLICATIONS INFORMATION
two poles in the loop. Rc provides a zero. With the recom-
mended output capacitor, the loop crossover occurs above
the R
C
C
C
zero. This simple model works well as long as the
value of the inductor is not too high and the loop crossover
frequency is much lower than the switching frequency.
With a larger ceramic capacitor that will have lower ESR,
crossover may be lower and a phase lead capacitor (C
PL
)
across the feedback divider may improve the transient
response. Large electrolytic capacitors may have an ESR
large enough to create an additional zero, and the phase
lead might not be necessary. If the output capacitor is
different than the recommended capacitor, stability should
be checked across all operating conditions, including DIM
and BRIGHT current modes, voltage control via FB, input
voltage, and temperature.
PCB Layout
For proper operation and minimum EMI, care must be taken
during printed circuit board layout. Figure 11 shows the
recommended component placement with trace, ground
plane, and via locations. Note that large, switched currents
fl ow in the LT3592’s V
IN
and SW pins, the catch diode (D1),
and the input capacitor (C2). The loop formed by these
components should be as small as possible and tied to
system ground in only one place. These components, along
with the inductor and output capacitor, should be placed on
the same side of the circuit board, and their connections
should be made on that layer. Place a local, unbroken ground
plane below these components, and tie this ground plane
to system ground at one location (ideally at the ground
terminal of the output capacitor C1). The SW and BOOST
nodes should be as small as possible. Finally, keep the
FB node small so that the ground pin and ground traces
will shield it from the SW and BOOST nodes. Include vias
near the exposed GND pad of the LT3592 to help remove
heat from the LT3592 to the ground plane.
High Temperature Considerations
The die temperature of the LT3592 must be lower than the
maximum rating of 125°C. This is generally not a concern
unless the ambient temperature is above 85°C. For higher
temperatures, extra care should be taken in the layout of
the circuit to ensure good heat sinking at the LT3592. The
maximum load current should be derated as the ambient
temperature approaches 125°C. The die temperature is
calculated by multiplying the LT3592 power dissipation
by the thermal resistance from junction to ambient.
Power dissipation within the LT3592 can be estimated
by calculating the total power loss from an effi ciency
measurement and subtracting the catch diode loss. The
resulting temperature rise at full load is nearly independent
of input voltage. Thermal resistance depends upon the
layout of the circuit board, but 76°C/W is typical for the
3mm × 2mm DFN (DDB10) package, and 38°C/W is typical
for the MS10E package.
Higher Output Voltages
At higher output voltages, the choice of output capacitor
becomes especially critical. Many small case size ceramic
capacitors lose much of their rated capacitance well below
Figure 11. A Good PCB Layout Ensures Proper, Low EMI Operation
3592 F11
SHDN
BRIGHT
V
IN
SYS GND
