89H48H12G2ZDBL Datasheet 89H48H12G2ZDBLG, 89H48H12G2ZCBLGI, 89H48H12G2ZDBLG8 | P7-P9

7 of 44 November 28, 2011

IDT 89HPES48H12G2 Data Sheet

Signal Type Name/Description

GPIO[0] I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

Alternate function pin name: PART0PERSTN

Alternate function pin type: Input/Output

Alternate function: Assertion of this signal initiated a partition fundamental

reset in the corresponding partition.

GPIO[1] I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

Alternate function pin name: PART1PERSTN

Alternate function pin type: Input/Output

Alternate function: Assertion of this signal initiated a partition fundamental

reset in the corresponding partition.

GPIO[2] I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

Alternate function pin name: PART2PERSTN

Alternate function pin type: Input/Output

Alternate function: Assertion of this signal initiated a partition fundamental

reset in the corresponding partition.

GPIO[3] I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

Alternate function pin name: PART3PERSTN

Alternate function pin type: Input/Output

Alternate function: Assertion of this signal initiated a partition fundamental

reset in the corresponding partition.

GPIO[4] I General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

1st Alternate function — Reserved

2nd Alternate function pin name: P0LINKUPN

2nd Alternate function pin type: Output

2nd Alternate function: Port 0 Link Up Status output.

GPIO[5] O General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

1st Alternate function pin name: GPEN

1st Alternate function pin type: Output

1st Alternate function: Hot-plug general purpose even output.

2nd Alternate function pin name: P0ACTIVEN

2nd Alternate function pin type: Output

2nd Alternate function: Port 0 Link Active Status Output.

GPIO[6] I General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

GPIO[7] I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

GPIO[8] I General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

Alternate function pin name: IOEXPINTN

Alternate function pin type: Input

Alternate function: IO expander interrupt.

Table 4 General Purpose I/O Pins

8 of 44 November 28, 2011

IDT 89HPES48H12G2 Data Sheet

Signal Type Name/Description

CLKMODE[2:0] Clock Mode. These signals determine the port clocking mode used by

ports of the device.

GCLKFSEL I Global Clock Frequency Select. These signals select the frequency of

the GCLKP and GCLKN signals.

0x0 100 MHz

0x1 125 MHz

P01MERGEN I Port 0 and 1 Merge. P01MERGEN is an active low signal. It is pulled low

internally. When this pin is low, port 0 is merged with port 1 to form a single

x8 port. The Serdes lanes associated with port 1 become lanes 4 through 7

of port 0. When this pin is high, port 0 and port 1 are not merged, and each

operates as a single x4 port.

P23MERGEN I Port 2 and 3 Merge. P23MERGEN is an active low signal. It is pulled low

internally. When this pin is low, port 2 is merged with port 3 to form a single

x8 port. The Serdes lanes associated with port 3 become lanes 4 through 7

of port 2. When this pin is high, port 2 and port 3 are not merged, and each

operates as a single x4 port.

P45MERGEN I Port 4 and 5 Merge. P45MERGEN is an active low signal. It is pulled low

internally. When this pin is low, port 4 is merged with port 5 to form a single

x8 port. The Serdes lanes associated with port 5 become lanes 4 through 7

of port 4. When this pin is high, port 4 and port 5 are not merged, and each

operates as a single x4 port.

P67MERGEN I Port 6 and 7 Merge. P67MERGEN is an active low signal. It is pulled low

internally. When this pin is low, port 6 is merged with port 7 to form a single

x8 port. The Serdes lanes associated with port 7 become lanes 4 through 7

of port 6. When this pin is high, port 6 and port 7 are not merged, and each

operates as a single x4 port.

P89MERGEN I Port 8 and 9 Merge. P89MERGEN is an active low signal. It is pulled low

internally. When this pin is low, port 8 is merged with port 9 to form a single

x8 port. The Serdes lanes associated with port 9 become lanes 4 through 7

of port 8. When this pin is high, port 8 and port 9 are not merged, and each

operates as a single x4 port.

P1213MERGEN I Port 12 and 13 Merge. P1213MERGEN is an active low signal. It is pulled

low internally. When this pin is low, port 12 is merged with port 13 to form a

single x8 port. The Serdes lanes associated with port 13 become lanes 4

through 7 of port 12. When this pin is high, port 12 and port 13 are not

merged, and each operates as a single x4 port.

Table 5 System Pins (Part 1 of 2)

9 of 44 November 28, 2011

IDT 89HPES48H12G2 Data Sheet

PERSTN I Global Reset. Assertion of this signal resets all logic inside PES48H12G2.

RSTHALT I Reset Halt. When this signal is asserted during a PCI Express fundamental

reset, PES48H12G2 executes the reset procedure and remains in a reset

state with the Master and Slave SMBuses active. This allows software to

read and write registers internal to the device before normal device opera-

tion begins. The device exits the reset state when the RSTHALT bit is

cleared in the SWCTL register by an SMBus master.

SWMODE[3:0] I Switch Mode. These configuration pins determine the PES48H12G2

switch operating mode. Note: These pins should be static and not change

following the negation of PERSTN.

0x0 - Single partition

0x1 - Single partition with Serial EEPROM initialization

0x2 through 0x7 - Reserved

0x8 - Single partition with port 0 selected as the upstream port (port 2 dis-

abled)

0x9 - Single partition with port 2 selected as the upstream port (port 0 dis-

abled)

0xA - Single partition with Serial EEPROM initialization and port 0 selected

as the upstream port (port 2 disabled)

0xB - Single partition with Serial EEPROM initialization and port 2 selected

as the upstream port (port 0 disabled)

0xC - Multi-partition

0xD - Multi-partition with Serial EEPROM initialization

0xE - Reserved

0xF - Reserved

Signal Type Name/Description

Table 5 System Pins (Part 2 of 2)

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P44

89H48H12G2ZDBL

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PCI Interface IC PCIE GEN2 SWITCH

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