10
LT1371
APPLICATIO S I FOR ATIO
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generates a loop “zero” at 5kHz to 50kHz that is instrumen-
tal in giving acceptable loop phase margin. Ceramic ca-
pacitors remain capacitive to beyond 300kHz and usually
resonate with their ESL before ESR becomes effective.
They are appropriate for input bypassing because of their
high ripple current ratings and tolerance of turn-on surges.
Output Diode
The suggested output diode (D1) is a 1N5821 Schottky or
its Motorola equivalent MBR330. It is rated at 3A average
forward current and 30V reverse voltage. Typical forward
voltage is 0.6V at 3A. The diode conducts current only
during switch OFF time. Peak reverse voltage for boost
converters is equal to regulator output voltage. Average
forward current in normal operation is equal to output
current.
Frequency Compensation
Loop frequency compensation is performed on the output
of the error amplifier (V
C
pin) with a series RC network.
The main pole is formed by the series capacitor and the
output impedance (500k) of the error amplifier. The
pole falls in the range of 2Hz to 20Hz. The series resistor
creates a “zero” at 1kHz to 5kHz, which improves loop
stability and transient response. A second capacitor, typi-
cally one-tenth the size of the main compensation capaci-
tor, is sometimes used to reduce the switching frequency
ripple on the V
C
pin. V
C
pin ripple is caused by output
voltage ripple attenuated by the output divider and multi-
plied by the error amplifier. Without the second capacitor,
V
C
pin ripple is:
V
C
Pin Ripple =
V
RIPPLE
= Output ripple (V
P–P
)
g
m
= Error amplifier transconductance
(1500µmho)
R
C
= Series resistor on V
C
pin
V
OUT
= DC output voltage
1.245(V
RIPPLE
)(g
m
)(R
C
)
(V
OUT
)
To prevent irregular switching, V
C
pin ripple should be
kept below 50mV
P–P
.
Worst-case V
C
pin ripple occurs at
Output Capacitor Ripple Current (RMS)
I
RIPPLE
(RMS) = I
OUT
= I
OUT
V
OUT
V
IN
V
IN
DC
1 – DC
DC = Switch Duty Cycle
Input Capacitors
The input capacitor of a boost converter is less critical due
to the fact that the input current waveform is triangular and
does not contain large squarewave currents as is found in
the output capacitor. Capacitors in the range of 10µF to
100µF, with an ESR of 0.2 or less, work well up to full 3A
switch current. Higher ESR capacitors may be acceptable
at low switch currents. Input capacitor ripple current for a
boost converter is :
I
RIPPLE
=
f = 500kHz Switching Frequency
0.3(V
IN
)(V
OUT
– V
IN
)
(f)(L)(V
OUT
)
The input capacitor can see a very high surge current when
a battery or high capacitance source is connected “live”
and solid tantalum capacitors can fail under this condition.
Several manufacturers have developed tantalum capaci-
tors specially tested for surge capability (AVX TPS series,
for instance) but even these units may fail if the input
voltage approaches the maximum voltage rating of the
capacitor during a high surge. AVX recommends derating
capacitor voltage by 2:1 for high surge applications.
Ceramic, OS-CON and aluminum electrolytic capacitors
may also be used and have a high tolerance to turn-on
surges.
Ceramic Capacitors
Higher value, lower cost ceramic capacitors are now
becoming available in smaller case sizes. These are tempt-
ing for switching regulator use because of their very low
ESR. Unfortunately, the ESR is so low that it can cause
loop stability problems. Solid tantalum capacitor ESR
11
LT1371
APPLICATIO S I FOR ATIO
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maximum output load current and will also be increased if
poor quality (high ESR) output capacitors are used. The
addition of a 0.0047µF capacitor on the V
C
pin reduces
switching frequency ripple to only a few millivolts. A low
value for R
C
will also reduce V
C
pin ripple, but loop phase
margin may be inadequate.
Layout Considerations
For maximum efficiency, LT1371 switch rise and fall times
are made as short as possible. To prevent radiation and
high frequency resonance problems, proper layout of the
components connected to the switch node is essential. B
field (magnetic) radiation is minimized by keeping output
diode, Switch pin and output bypass capacitor leads as
short as possible. Figures 3, 4 and 5 show recommended
positions for these components. E field radiation is kept
low by minimizing the length and area of all traces con-
nected to the Switch pin. A ground plane should always be
used under the switcher circuitry to prevent interplane
coupling.
The high speed switching current path is shown schemati-
cally in Figure 6. Minimum lead length in this path is
essential to ensure clean switching and low EMI. The path
including the switch, output diode and output capacitor is
the only one containing nanosecond rise and fall times.
Keep this path as short as possible.
V
IN
S/SGNDFB
V
SW
V
C
NFB
CONNECT
GROUND PIN 
AND TAB DIRECTLY
TO GROUND PLANE
C
D
KEEP PATH FROM 
V
SW
,
OUTPUT DIODE, 
OUTPUT CAPACITORS 
AND GROUND RETURN 
AS SHORT AS POSSIBLE
C
LT1371 • F03
Figure 3. Layout ConsiderationsR Package
V
IN
S/SGNDFB
V
SW
V
C
NFB
CONNECT
GROUND PIN 
AND TAB DIRECTLY
TO GROUND PLANE.
TAB MAY BE 
SOLDERED OR
BOLTED TO
GROUND PLANE*
C
D
KEEP PATH FROM 
V
SW
,
OUTPUT DIODE, 
OUTPUT CAPACITORS 
AND GROUND RETURN 
AS SHORT AS POSSIBLE
*SEE T7 PACKAGE LAYOUT CONSIDERATIONS FOR VERTICAL MOUNTING 
OF THE T7 PACKAGE
C
LT1371 • F04
Figure 4. Layout ConsiderationsT7 Package
Figure 6
LOAD
V
OUT
L1
SWITCH
NODE
LT1371 • F06
V
IN
HIGH
FREQUENCY
CIRCULATING
PATH
D
CONNECT ALL GROUND PINS TO GROUND PLANE
C
C
KEEP PATH FROM 
V
SW
,
OUTPUT DIODE, 
OUTPUT CAPACITORS 
AND GROUND RETURN 
AS SHORT AS POSSIBLE
LT1371 • F05
V
SW
NC
V
SW
GND
GND
GND
GND
NC
NC
GND
V
C
FB
NFB
GND
GND
GND
GND
SHDN
SYNC
V
IN
Figure 5. Layout ConsiderationsSW Package
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LT1371
APPLICATIO S I FOR ATIO
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LT1371T7
V
IN
V
IN
V
C
TAB
SYSTEM GROUND
FLOATING NODE
(TAB TIES INTERNALLY
TO PIN 4 GROUND)
4
21
5
7
GND GND
FB
LT1371 • F07
V
SW
V
OUT
Figure 7. Tab Connections for Vertically Mounted T7 Package
T7 Package Layout Considerations
Electrical connection to the tab of a T7 package is required
for proper device operation. If the tab is tied directly to the
ground plane (Figure 4) no other considerations are nec-
essary. If the tab is not connected directly to the ground
plane, as in a vertically mounted application, a separate
electrical connection from the tab to a “floating node” is
required. Ground returns for the V
IN
capacitor, V
C
compo-
nents and output feedback resistor divider are then con-
nected to the floating node. This is shown schematically in
Figure 7. All other system ground connections are made to
Pin 4.
The electrical connection from the T7 package tab to the
floating node must be a low resistance (<0.1), low
inductance (<20nH) path which can be accomplished with
a jumper wire or an electrically conductive heat sink.
Bolt the jumper wire directly to the tab using a solder tail
to maintain low resistance. The jumper wire length should
not exceed 3/4 inch of 24 AWG gauge wire or larger to
minimize the inductance.
Vertically mounted electrically conductive heat sinks are
available from many heat sink manufacturers. These heat
sinks also have tabs that solder directly to the board
creating the required low resistance, low inductance path
from the tab to the floating node. The tab should be bolted
or soldered directly to the heat sink to maintain low
resistance. Heat sinks are available in clip-on styles but are
only recommended if the tab to heat sink contact resis-
tance can be maintained below 0.1 for the life of the
product.
More Help
For more detailed information on switching regulator
circuits, please see Application Note 19. Linear Technol-
ogy also offers a computer software program,
SwitcherCAD, to assist in designing switching converters.
In addition, our Applications Department is always ready
to lend a helping hand.

LT1371IR#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 500kHz Hi Eff 3A Sw Reg
Lifecycle:
New from this manufacturer.
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