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ADM483JR-REEL7

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
5 V Low Power, Slew-Rate Limited
RS-485/RS-422 Transceiver
ADM483
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
FEATURES
EIA RS-485/RS-422-compliant
Data rates up to 250 kbps
Slew-rate limited for low EMI
100 nA supply current in shutdown mode
Low power consumption (120 µA)
Up to 32 transceivers on one bus
Outputs high-z when disabled or powered off
–7 V to +12 V bus common-mode range
Thermal shutdown and short-circuit protection
Pin-compatible with MAX483
Specified over –40°C to +85°C temperature range
Available in 8-lead SOIC package
APPLICATIONS
Low power RS-485 applications
EMI sensitive systems
DTE-DCE interfaces
Industrial control
Packet switching
Local area networks
Level translators
FUNCTIONAL BLOCK DIAGRAM
05079-001
RO
RE
R
DE
DI
D
A
B
GND
V
CC
ADM483
Figure 1.
GENERAL DESCRIPTION
The ADM483 is a low power differential line transceiver suitable
for half-duplex data communication on multipoint bus trans-
mission lines. It is designed for balanced data transmission, and
complies with EIA Standards RS-485 and RS-422.The part
contains a differential line driver and a differential line receiver.
Both share the same differential pins, with either the driver or
the receiver being enabled at any given time.
The device has an input impedance of 12 kΩ, allowing up to
32 transceivers on one bus. Since only one driver should be
enabled at any time, the output of a disabled or powered-down
driver is three-stated to avoid overloading the bus. This high
impedance driver output is maintained over the entire
common-mode voltage range from –7 V to +12 V.
The receiver contains a fail-safe feature that results in a logic
high output state if the inputs are unconnected (floating).
The driver outputs are slew-rate limited to reduce EMI and data
errors caused by reflections from improperly terminated buses.
Excessive power dissipation caused by bus contention or by
output shorting is prevented by a thermal shutdown circuit.
The part is fully specified over the industrial temperature range,
and is available in an 8-lead SOIC package.
ADM483
Rev. 0 | Page 2 of 16
TABLE OF CONTENTS
Specifications..................................................................................... 3
Timing Specifications....................................................................... 4
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Test Circ uits ....................................................................................... 7
Switching Characteristics ................................................................ 8
Typical Performance Characteristics ............................................. 9
Applications..................................................................................... 11
Differential Data Transmission ................................................ 11
Cable and Data Rate................................................................... 11
Thermal Shutdown .................................................................... 12
Receiver Open-Circuit Fail-Safe............................................... 12
Outline Dimensions ....................................................................... 13
Ordering Guide .......................................................................... 13
REVISION HISTORY
10/04—Revision 0: Initial Version
ADM483
Rev. 0 | Page 3 of 16
SPECIFICATIONS
V
CC
= 5 V ± 5%, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
DRIVER
Differential Output Voltage, V
OD
5 V
R = ∞, Figure 3
2.0 V R = 50 Ω (RS-422), Figure 3
1.5 5 V R = 27 Ω (RS-485), Figure 3
1.5 5 V V
TST
= –7 V to 12 V, Figure 4
∆ |V
OD
| for Complementary Output States 0.2 V R = 27 Ω or 50 Ω, Figure 3
Common-Mode Output Voltage, V
OC
3 V R = 27 Ω or 50 Ω, Figure 3
∆ |V
OC
| for Complementary Output States 0.2 V R = 27 Ω or 50 Ω, Figure 3
Output Short-Circuit Current, V
OUT
= High 35 250 mA –7 V < V
OUT
< +12 V
Output Short-Circuit Current, V
OUT
= Low 35 250 mA –7 V < V
OUT
< +12 V
DRIVER INPUT LOGIC
CMOS Input Logic Threshold Low 0.8 V
CMOS Input Logic Threshold High 2.0 V
CMOS Logic Input Current (DI) ±2 µA
DE Input Resistance to GND
220 kΩ
RECEIVER
Differential Input Threshold Voltage, V
TH
–200 +200 mV –7 V < V
CM
< +12 V
Input Hysteresis 70 mV V
CM
= 0V
Input Resistance (A, B) 12 kΩ –7 V < V
CM
< +12 V
Input Current (A, B)
1 mA V
IN
= +12 V
–0.8 mA V
IN
= –7 V
CMOS Logic Input Current (RE)
±2 µA
CMOS Output Voltage Low 0.4 V I
OUT
= 4 mA
CMOS Output Voltage High 3.5 V I
OUT
= –4 mA
Output Short-Circuit Current 7 95 mA 0 V < V
OUT
< V
CC
Three-State Output Leakage Current ±2 µA 0.4 ≤ V
OUT
≤ 2.4 V
POWER SUPPLY CURRENT 0.1 10 µA
DE = 0 V,
RE = V
CC
(shutdown)
120 250 µA
DE = 0 V,
RE = 0 V
350 650 µA DE = V
CC
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

ADM483JR-REEL7

Mfr. #:
Buy ADM483JR-REEL7
Manufacturer:
Analog Devices Inc.
Description:
RS-422/RS-485 Interface IC S/Rate EMC Compliant RS485 Tranciever IC
Lifecycle:
New from this manufacturer.
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