AD8230
Rev. B | Page 12 of 16
TEMPERATURE (°C)
150–50 0 50 100
OFFSET VOLTAGE (µV RTI)
0
–1
–2
–3
–4
–5
R
F
= 100kΩ, R
G
= 1kΩ
R
F
= 10kΩ, R
G
= 100Ω
05063-033
Figure 33. Effect of Feedback Resistor on Offset Voltage Drift
LEVEL-SHIFTING THE OUTPUT
A reference voltage, as shown in Figure 34, can be used to
level-shift the output. The reference voltage, V
R
, is limited to
−V
S
+ 3.5 V to +V
S
− 2.5 V. (For G < 10, the reference voltage
range is limited to −V
S
+ 4.24 V to +V
S
– 2.75 V.) Otherwise, it
is nominally tied to midsupply. The voltage source used to level-
shift the output should have a low output impedance to avoid
contributing to gain error. In addition, it should be able to
source and sink current. To minimize offset voltage, the V
REF
pins should be connected either to the local ground or to a
reference voltage source that is connected to the local ground.
2
6
1
7
5
8
4
3
AD8230
V
OUT
–V
S
+
S
0.1µF
R
G
R
F
0.1µF
V
R
05063-034
Figure 34. Level-Shifting the Output
The output can also be level-shifted by adding a resistor, R
O
, as
shown in
Figure 35. The benefit is that the output can be level-
shifted to as low as 100 mV of the negative supply rail and to as
high as 200 mV of the positive supply rail, increasing unipolar
output swing. This can be useful in applications, such as strain
gauges, where the force is only applied in one direction. Another
benefit of this configuration is that a supply rail can be used for
V
R’
eliminating the need to add an additional external reference
voltage.
The gain changes with the inclusion of R
O
. The full expression is
()
'
R
O
F
IN
OG
OG
F
R'
O
F
IN
OG
F
OUT
V
R
R
V
RR
RRR
V
R
R
V
RR
R
V −
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
+
+
=−
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
+= 121
||
2
(3)
The following steps can be taken to set the gain and level-shift
the output:
1.
Select an R
F
value. Table 5 shows R
F
values for various gains.
2.
Solve for R
O
using Equation 4.
LEVEL
DESIRED
F
R'
O
V
RV
R
−
−= (4)
where:
V
R’
is a voltage source, such as a supply voltage.
V
DESIRED-LEVEL
is the desired output bias voltage.
3.
Solve for R
G
.
11
2
−
⎟
⎠
⎞
⎜
⎝
⎛
−
=
F
O
O
G
R
R
Gain
R
R
(5)
2
6
1
7
5
8
4
3
AD8230
V
OUT
–V
S
+
S
0.1µF
R
G
R
F
R
O
0.1µF
V
R
'
5063-035
Figure 35. Level-Shifting the Output Without an
Additional Voltage Reference
2
6
1
7
5
8
4
3
AD8230
V
OUT
–5V
+5
0.1µF
203Ω
9.76kΩ
10.2kΩ
0.1µF
+5V
5063-036
Figure 36. An AD8230 with its Output Biased at −4.8 V;
G = 100; V
DESIRED-LEVEL
= −4.8 V
SOURCE IMPEDANCE AND INPUT SETTLING TIME
The input stage of the AD8230 consists of two actively driven,
differential switched capacitors, as described in
Figure 30 and
Figure 31. Differential input signals are sampled on C
SAMPLE
such
that the associated parasitic capacitances, 70 pF, are balanced
between the inputs to achieve high common-mode rejection.
On each sample period (approximately 85 μs), these parasitic
capacitances must be recharged to the common-mode voltage
by the signal source impedance (10 kΩ maximum). If resistors
and capacitors are used at the input of the AD8230, care should
be taken to maintain close match to maximize CMRR.
