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AD538BDZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
AD538
Rev. E | Page 9 of 16
THEORY OF OPERATION
RE-EXAMINATION OF MULTIPLIER/DIVIDER ACCURACY
Traditionally, the accuracy (actually the errors) of analog
multipliers and dividers has been specified in terms of percent
of full scale. Thus specified, a 1% multiplier error with a 10 V
full-scale output would mean a worst-case error of +100 mV at
any level within its designated output range. While this type of
error specification is easy to test evaluate, and interpret, it can
leave the user guessing as to how useful the multiplier actually
is at low output levels, those approaching the specified error
limit (in this case) 100 mV.
The error sources of the AD538 do not follow the percent of
full-scale approach to specification, thus it more optimally
fits the needs of the very wide dynamic range applications
for which it is best suited. Rather than as a percent of full
scale, the AD538’s error as a multiplier or divider for a 100:1
(100 mV to 10 V) input range is specified as the sum of two
error components: a percent of reading (ideal output) term
plus a fixed output offset. Following this format, the AD538AD,
operating as a multiplier or divider with inputs down to 100 mV,
has a maximum error of ±1% of reading ±500 μV. Some sample
total error calculations for both grades over the 100:1 input
range are illustrated in Table 4. This error specification format
is a familiar one to designers and users of digital voltmeters
where error is specified as a percent of reading ± a certain
number of digits on the meter readout.
For operation as a multiplier or divider over a wider dynamic
range (>100:1), the AD538 has a more detailed error specification
that is the sum of three components: a percent of reading term,
an output offset term, and an input offset term for the V
Y
/V
X
log
ratio section. A sample application of this specification, taken
from Table 4, for the AD538AD with V
Y
= 1 V, V
Z
= 100 mV
and V
X
= 10 mV would yield a maximum error of ±2.0% of
reading ±500 μV ± (1 V + 100 mV)/10 mV × 250 μV or ±2.0%
of reading ±500 μV ± 27.5 mV. This example illustrates that
with very low level inputs the AD538’s incremental gain (V
Y
+
V
Z
)/V
X
has increased to make the input offset contribution to
error substantial.
Table 4. Sample Error Calculation Chart (Worst Case)
V
Y
Input
(V)
V
Z
Input
(V)
V
X
Input
(V)
Ideal
Output
(V)
Total O ffset Error
Term (mV)
% of Reading
Error Term
(mV)
Total Error
Summation
(mV)
Total Error
Summation as a
% of the Ideal
Output
100:1 INPUT
RANGE
Total Error =
±% rdg
±Output V
OS
10 10 10 10 0.5 (AD) 100 (AD) 100.5 (AD) 1.0 (AD)
0.25 (BD) 50 (BD) 50.25 (BD) 0.5 (BD)
10 0.1 0.1 10 0.5 (AD) 100 (AD) 100.5 (AD) 1.0 (AD)
0.25 (BD) 50 (BD) 50.25 (BD) 0.5 (BD)
1 1 1 1 0.5 (AD) 10 ) (AD 10.5 (AD) 1.05 (AD)
0.25 (BD) 5 (BD) 5.25 (BD) 0.5 (BD)
0.1 0.1 0.1 0.1 0.5 (AD) 1 (AD) 1.5 (AD) 1.5 (AD)
0.25 (BD) 0.5 (BD) 0.75 (BD) 0.75 (BD)
WIDE
DYNAMIC
RANGE
Total Error =
±% rdg ±
Output V
OS
±
Input V
OS
×
(V
Y
+ V
Z
)/V
X
1 0.10 0.01 10 28 (AD) 200 (AD) 228 (AD) 2.28 (AD)
16.75 (BD) 100 (BD) 116.75 (BD) 1.17 (BD)
10 0.05 2 0.25 1.76 (AD) 5 (AD) 6.76 (AD) 2.7 (AD)
1 (BD) 2.5 (BD) 3.5 (BD) 1.4 (BD)
5 0.01 0.01 5 125.75 (AD) 100 (AD) 225.75 (AD) 4.52 (AD)
75.4 (BD) 50 (BD) 125.4 (BD) 2.51 (BD)
10 0.01 0.1 1 25.53 (AD) 20 (AD) 45.53 (AD) 4.55 (AD)
15.27 (BD) 10 (BD) 25.27 (BD) 2.53 (BD)
AD538
Rev. E | Page 10 of 16
FUNCTIONAL DESCRIPTION
As shown in Figure 1 and Figure 11, the V
Z
and V
X
inputs
connect directly to the input log ratio amplifiers of the AD538.
This subsection provides an output voltage proportional to the
natural log of input voltage, V
Z
, minus the natural log of input
voltage, V
X
. The output of the log ratio subsection at B can be
expressed by the transfer function
=
X
Z
B
V
V
q
kT
V ln
where:
k is 1.3806 × 10
−23
J/K.
q is 1.60219 × 10
−19
C.
T is in Kelvins.
The log ratio configuration may be used alone, if correctly
temperature compensated and scaled to the desired output
level (see the Applications Information section).
Under normal operation, the log-ratio output will be directly
connected to a second functional block at Input C, the antilog
subsection. This section performs the antilog according to the
transfer function:
=
kT
q
VeVV
C
Y
O
As with the log-ratio circuit included in the AD538, the user
may use the antilog subsection by itself. When both subsections
are combined, the output at B is tied to C, the transfer function
of the AD538 computational unit is:
V
O
= V
Y
e
C
B
V
V
kT
q
Q
kT
VV
X
Z
=
;
ln
which reduces to:
=
X
Z
Y
O
V
V
VV
Finally, by increasing the gain, or attenuating the output of the
log ratio subsection via resistor programming, it is possible to
raise the quantity V
Z
/V
X
to the m
th
power. Without external
programming, m is unity. Thus, the overall AD538 transfer
function equals:
m
X
Z
Y
O
V
V
VV
=
where 0.2 < m < 5.
When the AD538 is used as an analog divider, the V
Y
input can
be used to multiply the ratio V
Z
/V
X
by a convenient scale factor.
The actual multiplication by the V
Y
input signal is accomplished
by adding the log of the V
Y
input signal to the signal at C, which
is already in the log domain.
STABILITY PRECAUTIONS
At higher frequencies, the multistaged signal path of the AD538
can result in large phase shifts (as illustrated in Figure 11). If a
condition of high incremental gain exists along that path (for
example, V
O
= V
Y
× V
Z
/V
X
= 10 V × 10 mV/10 mV = 10 V so
that ΔV
O
/ΔV
X
= 1000), then small amounts of capacitive feedback
from V
O
to the current inputs I
Z
or I
X
can result in instability.
Appropriate care should be exercised in board layout to prevent
capacitive feedback mechanisms under these conditions.
00959-012
LOG
e
I
Y
V
Y
Ln Y
LOG
e
I
Z
V
Z
Ln Z
LOG
e
I
X
V
X
Ln X
ΣΣ
BUFFER
+
++
–
Ln Z – Ln X
M(Ln Z – Ln X)
M(Ln Z – Ln X) +Ln Y
ANTILOG
e
0.2≤M≤5
V
O
= V
Y
V
Z
V
X
M
Figure 11. Model Circuit
USING THE VOLTAGE REFERENCES
A stable band gap voltage reference for scaling is included in the
AD538. It is laser-trimmed to provide a selectable voltage output of
+10 V buffered (Pin 4), +2 V unbuffered (Pin 5) or any voltages
between +2 V and +10.2 V buffered as shown in Figure 12. The
output impedance at Pin 5 is approximately 5 kΩ. Note that any
loading of this pin produces an error in the +10 V reference
voltage. External loads on the +2 V output should be greater
than 500 kΩ to maintain errors less than 1%.
25kΩ
25kΩ
100Ω
25kΩ
25kΩ
ANTILOG
LOG
OUTPUT
100Ω
50kΩ
+2V TO +10.2V
BUFFERED
11.5kΩ
AD538
I
Y
A
D
I
X
V
X
C
V
Y
811
17
16
15
14
13
12
11
10
2
3
4
5
6
7
8
9
LOG
RATIO
INTERNAL
VOLTAGE
REFERENCE
SIGNAL
GND
PWR
GND
I
Z
V
Z
V
O
I
+V
S
–V
S
B
REF OUT
+2V
00959-013
Figure 12. +2 V to +10.2 V Adjustable Reference
In situations not requiring both reference levels, the +2 V output
can be converted to a buffered output by tying Pin 4 and Pin 5
together. If both references are required simultaneously, the
+10 V output should be used directly and the +2 V output
should be externally buffered.
AD538
Rev. E | Page 11 of 16
ONE-QUADRANT MULTIPLICATION/DIVISION
Figure 13 shows how the AD538 may be easily configured
as a precision one-quadrant multiplier/divider. The transfer
function V
O
= V
Y
(V
Z
/V
X
) allows three independent input
variables, a calculation not available with a conventional
multiplier. In addition, the 1000:1 (that is, 10 mV to 10 V)
input dynamic range of the AD538 greatly exceeds that of
analog multipliers computing one-quadrant multiplication
and division.
25kΩ
25kΩ
100Ω
25kΩ
25kΩ
ANTILOG
LOG
OUTPUT
100Ω
AD538
I
Y
A
D
I
X
V
X
C
IN4148
V
Y
811
17
16
15
14
13
12
11
10
2
3
4
5
6
7
8
9
LOG
RATIO
INTERNAL
VOLTAGE
REFERENCE
SIGNAL
GND
PWR
GND
I
Z
V
Z
V
Z
INPUT
V
O
I
+15V
–15V
B
+10V
+2V
00959-014
OUTPUT
V
Y
INPUT
V
X
INPUT
V
O
= V
Y
V
Z
V
X
Figure 13. One-Quadrant Combination Multiplier/Divider
By simply connecting the input, V
X
(Pin 15) to the 10 V
reference (Pin 4), and tying the log-ratio output at B to the
antilog input at C, the AD538 can be configured as a one-
quadrant analog multiplier with 10 V scaling. If 2 V scaling
is desired, V
X
can be tied to the 2 V reference.
When the input V
X
is tied to the +10 V reference terminal, the
multiplier transfer function becomes:
=
V
V
VV
Z
Y
O
10
As a multiplier, this circuit provides a typical bandwidth of 400 kHz
with values of V
X
, V
Y
, or V
Z
varying over a 100:1 range (that is,
100 mV to 10 V). The maximum error with a 100 mV to 10 V
range for the two input variables will typically be +0.5% of
reading. Using the optional Z offset trim scheme, as shown in
Figure 14, this error can be reduced to +0.25% of reading.
By using the 10 V reference as the V
Y
input, the circuit of
Figure 13 is configured as a one-quadrant divider with a fixed
scale factor. As with the one-quadrant multiplier, the inputs
accept only single (positive) polarity signals. The output of the
one-quadrant divider with a +10 V scale factor is:
=
X
Z
O
V
V
VV 10
The typical bandwidth of this circuit is 370 kHz with 1 V to
10 V denominator input levels. At lower amplitudes, the band-
width gradually decreases to approximately 200 kHz at the
2 mV input level.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

AD538BDZ

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Manufacturer:
Analog Devices Inc.
Description:
Special Purpose Amplifiers MULT/DIV ACU IC
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