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CY2SSTV857ZXC-32

P1-P3P4-P6P7-P8
Differential Clock Buffer/Driver DDR400/PC3200-Compliant
CY2SSTV857-32
..........................Document #: 38-07557 Rev. *E Page 1 of 8
400 West Cesar Chavez, Austin, TX 78701 1+(512) 416-8500 1+(512) 416-9669 www.silabs.com
Features
• Operating frequency: 60 MHz to 230 MHz
• Supports 400 MHz DDR SDRAM
• 10 differential outputs from one differential input
• Spread-Spectrum-compatible
• Low jitter (cycle-to-cycle): < 75
• Very low skew: < 100 ps
• Power management control input
• High-impedance outputs when input clock < 20 MHz
• 2.6V operation
• Pin-compatible with CDC857-2 and -3
• 48-pin TSSOP and 40 QFN package
• Industrial temperature of –40°C to 85°C
• Conforms to JEDEC DDR specification
Description
The CY2SSTV857-32 is a high-performance, low-skew,
low-jitter zero-delay buffer designed to distribute differential
clocks in high-speed applications. The CY2SSTV857-32
generates ten differential pair clock outputs from one differ-
ential pair clock input. In addition, the CY2SSTV857-32
features differential feedback clock outpts and inputs. This
allows the CY2SSTV857-32 to be used as a zero delay buffer.
When used as a zero delay buffer in nested clock trees, the
CY2SSTV857-32 locks onto the input reference and translates
with near-zero delay to low-skew outputs.
Block Diagram Pin Configuration
3
2
5
6
10
9
20
19
22
23
46
47
44
43
39
40
29
30
27
26
32
33
Y0
Y0#
Y1
Y1#
Y2
Y2#
Y3
Y3#
Y4
Y4#
Y5
Y5#
Y6
Y6#
Y7
Y7#
Y8
Y8#
Y9
Y9#
FBOUT
FBOUT#
Test and
Powerdown
Logic
PLL
13
14
36
35
FBIN
FBIN#
CLK
CLK#
AVDD
37
16
PD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
VSS
Y0#
Y0
VDDQ
Y1
Y1#
VSS
VSS
Y2#
Y2
VDDQ
VDDQ
CLK
CLK#
VDDQ
AVDD
AVSS
VSS
Y3#
Y3
VDDQ
Y4
Y4#
VSS
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VSS
Y5#
Y5
VDDQ
Y6
Y6#
VSS
VSS
Y7#
Y7
VDDQ
PD#
FBIN
FBIN#
VDDQ
FBOUT#
FBOUT
VSS
Y8#
Y8
VDDQ
Y9
Y9#
VSS
CY2SSTV857-32
CY2SSTV857
..........................Document #: 38-07557 Rev. *E Page 2 of 8
Pin Description
Pin #
48 TSSOP
Pin #
40 QFN Pin Name I/O
[1]
Pin Description
Electrical
Characteristics
13, 14 5,6 CLK, CLK# I Differential Clock Input. LV Differential Input
35 25 FBIN# I Feedback Clock Input. Connect to FBOUT# for
accessing the PLL.
Differential Input
36 26 FBIN I Feedback Clock Input. Connect to FBOUT for
accessing the PLL.
3, 5, 10, 20, 22 37,39,3,12,14 Y(0:4) O Clock Outputs. Differential Outputs
2, 6, 9, 19, 23 36,40,2,11,15 Y#(0:4) O Clock Outputs.
27, 29, 39, 44, 46 17,19,29,32,34 Y(9:5) O Clock Outputs. Differential Outputs
26, 30, 40, 43, 47 16,20,30,31,35 Y#(9:5) O Clock Outputs.
32 21 FBOUT O Feedback Clock Output. Connect to FBIN for
normal operation. A bypass delay capacitor at
this output will control Input Reference/Output
Clocks phase relationships.
Differential Outputs
33 22 FBOUT# O Feedback Clock Output. Connect to FBIN# for
normal operation. A bypass delay capacitor at
this output will control Input Reference/Output
Clocks phase relationships.
37 27 PD# I Power Down Input. When PD# is set HIGH, all
Q and Q# outputs are enabled and switch at the
same frequency as CLK. When set LOW, all Q
and Q# outputs are disabled Hi-Z and the PLL
is powered down.
4, 11,12,15, 21,
28, 34, 38, 45
4,7,13,18,23,24,
28,33,38
VDDQ 2.6V Power Supply for Output Clock Buffers.2.6V Nominal
16 8 AVDD 2.6V Power Supply for PLL. When VDDA is at
GND, PLL is bypassed and CLK is buffered
directly to the device outputs. During disable
(PD# = 0), the PLL is powered down.
2.6V Nominal
1, 7, 8, 18, 24, 25,
31, 41, 42, 48
1,10 VSS Common Ground. 0.0V Ground
17 9 AVSS Analog Ground.0.0V Analog
Ground
Note:
1. A bypass capacitor (0.1F) should be placed as close as possible to each positive power pin (<0.2”). If these bypass capacitors are not close to the pins, their
high-frequency filtering characteristic will be cancelled by the lead inductance of the traces.
40 QFN
CY2SSTV857-32
19
1817
161514
1312
11
20
Y3#
y3
VDDQ
Y4
Y4#
Y9#
Y9
VDDQ
Y8
Y8#
32
3334
353637
3839
40
31
Y1#
Y1
VDDQ
Y0
Y0#
Y5#
Y5
VDDQ
Y6
Y6#
30
29
28
27
26
25
24
23
22
21
Y7#
VDDQ
Y7
PD#
FBIN
FBIN#
VDDQ
VDDQ
FBOUT#
FBOUT
1
2
3
4
5
6
7
8
9
10
VSS
Y2
Y2#
VDDQ
CLK
CLK#
VDDQ
AVDD
AVSS
VSS
40 QFN Package
CY2SSTV857
..........................Document #: 38-07557 Rev. *E Page 3 of 8
Zero Delay Buffer
When used as a zero delay buffer the CY2SSTV857-32 will
likely be in a nested clock tree application. For these applica-
tions, the CY2SSTV857-32 offers a differential clock input pair
as a PLL reference. The CY2SSTV857-32 then can lock onto
the reference and translate with near zero delay to low-skew
outputs. For normal operation, the external feedback input,
FBIN, is connected to the feedback output, FBOUT. By
connecting the feedback output to the feedback input the
propagation delay through the device is eliminated. The PLL
works to align the output edge with the input reference edge
thus producing a near zero delay. The reference frequency
affects the static phase offset of the PLL and thus the relative
delay between the inputs and outputs.
When VDDA is strapped LOW, the PLL is turned off and
bypassed for test purposes.
Power Management
Output enable/disable control of the CY2SSTV857-32 allows
the user to implement power management schemes into the
design. Outputs are three-stated/disabled when PD# is
asserted LOW (see Table 1).
Table 1. Function Table
Inputs Outputs
PLLAVDD PD# CLK CLK# Y Y# FBOUT FBOUT#
GND H L H L H L H BYPASSED/OFF
GND H H L H L H L BYPASSED/OFF
XL L HZ Z ZZ Off
XL H LZ Z ZZ OFF
2.6V H L H L H L H On
2.6V H H L H L H L On
2.6V H < 20 MHz < 20 MHz Hi-Z Hi-Z Hi-Z HI-Z Off
Figure 1. Phase Error and Skew Waveforms
P1-P3P4-P6P7-P8

CY2SSTV857ZXC-32

Mfr. #:
Buy CY2SSTV857ZXC-32
Manufacturer:
Silicon Labs
Description:
Clock Buffer 2.5V,60-200MHz,1:10 Diff DDR266/333 Buffer/Driver
Lifecycle:
New from this manufacturer.
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