AD7249
–3
TIMING CHARACTERISTICS
1, 2
Limit at T
MIN
to T
MAX
Parameter (All Versions) Unit Conditions/Comments
t
1
4
200 ns min SCLK Cycle Time
t
2
15 ns min SYNC to SCLK Falling Edge Setup Time
t
3
50 ns min SYNC to SCLK Hold Time
t
4
0 ns min Data Setup Time
t
5
150 ns min Data Hold Time
t
6
0 ns min SYNC High to LDAC Low
t
7
20 ns min LDAC Pulsewidth
t
8
0 ns min LDAC High to SYNC Low
t
9
50 ns min CLR Pulsewidth
t
10
20 ns min SYNC High Time
NOTES
1
Timing specifications guaranteed by design not production tested. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage
level of 1.6 V.
2
See Figure 8.
3
Power supply tolerance, A Version: ± 10%; B, S Versions: ± 5%.
4
SCLK Mark/Space Ratio range is 45/55 to 55/45.
(V
DD
= +12 V to +15 V,
3
V
SS
= 0 V or –12 V to –15 V,
3
AGND = DGND = 0 V, R
L
= 2 k,
C
L
= 100 pF. All specifications T
MIN
to T
MAX
unless otherwise noted.)
ABSOLUTE MAXIMUM RATINGS
1
(T
A
= +25°C unless otherwise noted)
V
DD
to AGND, DGND . . . . . . . . . . . . . . . . . . –0.3 V to +17 V
V
SS
to AGND, DGND . . . . . . . . . . . . . . . . . . +0.3 V to –17 V
AGND to DGND . . . . . . . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
V
OUTA, B
2
to AGND . . . . . . . . . . . . V
SS
– 0.3 V to V
DD
+ 0.3 V
REFOUT to AGND . . . . . . . . . . . . . . . . . . . . . . . . 0 V to V
DD
REFIN to AGND . . . . . . . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
Digital Inputs to DGND . . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
Operating Temperature Range
Industrial (A, B Versions) . . . . . . . . . . . . . . –40°C to +85°C
Extended (S Version) . . . . . . . . . . . . . . . . . –55°C to +125°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Power Dissipation Plastic DIP . . . . . . . . . . . . . . . . . . . 600 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . +117°C/W
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . +300°C
Power Dissipation, Cerdip . . . . . . . . . . . . . . . . . . . . . . 600 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 76°C/W
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . +300°C
Power Dissipation, SOIC . . . . . . . . . . . . . . . . . . . . . . . 600 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 75°C/W
Lead Temperature (Soldering)
Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one Absolute
Maximum Rating may be applied at any time.
2
The outputs may be shorted to voltages in this range provided the power dissipation
of the package is not exceeded.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7249 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
AD7249
PIN FUNCTION DESCRIPTION (DIP & SOIC PIN NUMBERS)
Pin Mnemonic Description
11 REFOUT Voltage Reference Output. The internal 5 V analog reference is provided at this pin. To operate the
part using its internal reference, REFOUT should be connected to REFIN.
12 REFIN Voltage Reference Input. It is internally buffered before being applied to both DACs. The nominal
reference voltage for specified operation of the AD7249 is 5 V.
13R
OFSB
Output Offset Resistor for the amplifier of DAC B. It is connected to V
OUTB
for the +5 V range, to
AGND for the +10 V range and to REFIN for the –5 V to +5 V range.
14V
OUTB
Analog Output Voltage of DAC B. This is the buffer amplifier output voltage. Three different output
voltage ranges can be chosen: 0 V to +5 V, 0 V to +10 V and –5 V to +5 V.
15 AGND Analog Ground. Ground reference for all analog circuitry.
16 CLR Clear, Logic Input. Taking this input low clears both DACs. It sets V
OUTA
and V
OUTB
to 0 V in both
unipolar ranges and the twos complement bipolar range and to –REFIN in the offset binary bipolar
range.
17 BIN/COMP Logic Input. This input selects the data format to be either binary or twos complement. In both uni-
polar ranges natural binary format is selected by connecting this input to a Logic “0”. In the bipolar
configuration offset binary format is selected with a Logic “0” while a Logic “1” selects twos complement.
18 DGND Digital Ground. Ground reference for all digital circuitry.
19 SDIN Serial Data In, Logic Input. The 16-bit serial data word is applied to this input.
10 LDAC Load DAC, Logic Input. Updates both DAC outputs. The DAC outputs are updated on the falling
edge of this signal or alternatively if this line is permanently low, an automatic update mode is se-
lected whereby both DACs are updated on the 16th falling SCLK pulse.
11 SCLK Serial Clock, Logic Input. Data is clocked into the input register on each falling SCLK edge.
12 SYNC Data Synchronization Pulse, Logic Input. Taking this input low initializes the internal logic in readi-
ness for a new data word.
13 V
DD
Positive Power Supply.
14 V
OUTA
Analog Output Voltage of DAC A. This is the buffer amplifier output voltage. Three different output
voltage ranges can be chosen: 0 V to +5 V, 0 V to +10 V and –5 V to +5 V.
15 V
SS
Negative Power Supply (used for the output amplifier only) may be connected to 0 V for single sup-
ply operation or –12 V to –15 V for dual supplies.
16 R
OFSA
Output Offset Resistor for the amplifier of DAC A. It is connected to V
OUTA
for the +5 V range, to
AGND for the +10 V range and to REFIN for the –5 V to +5 V range.
PIN CONFIGURATIONS
(DIP and SOIC)
TOP VIEW
(Not to Scale)
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
REFOUT R
OFSA
AD7249
REFIN V
SS
R
OFSB
V
OUTA
V
OUTB
V
DD
AGND
SYNC
CLR
SCLK
BIN/COMP LDAC
DGND SDIN
REV. D
AD7249
–5
TERMINOLOGY
Bipolar Zero Error
Bipolar Zero Error is the voltage measured at V
OUT
when the
DAC is configured for bipolar output and loaded with all 0s
(Twos Complement Coding) or with 1000 0000 0000 (Offset
Binary Coding). It is due to a combination of offset errors in the
DAC, amplifier and mismatch between the internal gain resis-
tors around the amplifier.
Full-Scale Error
Full-Scale Error is a measure of the output error when the am-
plifier output is at full scale (for the bipolar output range full
scale is either positive or negative full scale). It is measured with
respect to the reference input voltage and includes the offset
errors.
Digital-to-Analog Glitch Impulse
This is the voltage spike that appears at V
OUT
when the digital
code in the DAC Latch changes, before the output settles to its
final value. It is normally specified as the area of the glitch in
nV-secs and is measured when the digital code is changed by
1 LSB at the major carry transition (0111 1111 1111 to 1000
0000 0000 or 1000 0000 0000 to 0111 1111 1111).
Digital Feedthrough
This is a measure of the voltage spike that appears on V
OUT
as a
result of feedthrough from the digital inputs on the AD7249. It
is measured with LDAC held high.
Relative Accuracy (Linearity)
Relative Accuracy, or endpoint linearity, is a measure of the
maximum deviation of the DAC transfer function from a
straight line passing through the endpoints of the transfer func-
tion. It is measured after allowing for zero and full-scale errors
and is expressed in LSBs or as a percentage of full-scale reading.
Single Supply Linearity and Gain Error
The output amplifier on the AD7249 can have true negative
offsets even when the part is operated from a single +15 V sup-
ply. However, because the negative supply rail (V
SS
) is 0 V, the
output cannot actually go negative. Instead, when the output
offset voltage is negative, the output voltage sits at 0 V, resulting
in the transfer function shown in Figure 1.
DAC CODE
OUTPUT
VOLTAGE
NEGATIVE
OFFSET
0V
Figure 1. Effect of Negative Offset (Single Supply)
This “knee” is an offset effect, not a linearity error, and the
transfer function would have followed the dotted line if the
output voltage could have gone negative.
Normally, linearity is measured between zero (all 0s input code)
and full scale (all 1s input code) after offset and full scale have
been adjusted out or allowed for, but this is not possible in
single supply operation if the offset is negative, due to the knee
in the transfer function. Instead, linearity of the AD7249 in the
unipolar mode is measured between full scale and the lowest
code which is guaranteed to produce a positive output voltage.
This code is calculated from the maximum specification for
negative offset. For the A and B versions, the linearity is mea-
sured between Codes 3 and 4095. For the S grade, linearity is
measured between Code 5 and Code 4095.
Differential Nonlinearity
Differential Nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ± 1 LSB or less
over the operating temperature range ensures monotonicity.
Unipolar Offset Error
Unipolar Offset Error is the measured output voltage from V
OUT
with all zeros loaded into the DAC latch, when the DAC is
configured for unipolar output. It is due to a combination of the
offset errors in the DAC and output amplifier.
CIRCUIT INFORMATION
D/A Section
The AD7249 contains two 12-bit voltage-mode D/A converters
consisting of highly stable thin film resistors and high-speed
NMOS single-pole, double-throw switches. The simplified
circuit diagram for the DAC section is shown in Figure 2. The
output voltage from the converter has the same polarity as the
reference voltage, REFIN, allowing single supply operation.
2R 2R
2R 2R 2R 2R 2R 2R
R RRRR
REFIN*
AGND
*BUFFERED REFIN VOLTAGE
R
OFS
V
OUT
SHOWN FOR ALL 1s
ON DAC
Figure 2. D/A Simplified Circuit Diagram

AD7249BR-REEL

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC LC2MOS DUAL 12-BIT SERIAL IC
Lifecycle:
New from this manufacturer.
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