Input Voltage for RESET2 Monitor. High-impedance input for internal reset
comparator. Connect this pin to an external resistive-divider network to set the reset
threshold voltage.
22V
CC
Supply Voltage and Input Voltage for Primary Supply Monitor
33CSRT
RESET2 Delay Set Capacitor. Connect to V
CC
for a fixed 140ms (min) timeout period
or to an external capacitor for a user-adjustable timeout period after V
CC
exceeds its
minimum threshold.
44GND Ground
55RESET2
Secondary Reset Output, Open-Drain, Active-Low. RESET2 changes from high to low
when either V
CC
or RESET IN2 drop below their thresholds. RESET2 remains low for a
user-adjustable timeout period (see CSRT) or a fixed 140ms (min) after V
CC
and
RESET IN2 meet their minimum thresholds.
66R2
47kΩ Internal Pullup Resistor for RESET2. Connect to external voltage for RESET2
high pullup.
77RESET1
Primary Reset Output, Open-Drain (MAX6391) or Push-Pull (MAX6392), Active-Low.
RESET1 changes from HIGH to LOW when the V
CC
input drops below the selected
reset threshold. RESET1 remains LOW for the reset timeout period after V
CC
exceeds
the minimum threshold.
8—R1
47kΩ Internal Pullup Resistor for RESET1. Connect to external voltage for RESET1
high pullup.
—8MR
Manual Reset, Active-Low, Internal 47kΩ Pullup to V
CC
. Pull LOW to force a reset.
RESET1 and RESET2 remain asserted as long as MR is LOW and for the RESET1 and
Detailed Description
Each device includes a pair of voltage monitors with
sequenced reset outputs. The first block monitors V
CC
only (RESET1 output is independent of the RESET IN2
monitor). It asserts a reset signal (LOW) whenever V
CC
is below the preset voltage threshold. RESET1 remains
asserted for at least 140ms after V
CC
rises above the
reset threshold. RESET1 timing is internally set in each
device. V
CC
voltage thresholds are available from
1.57V to 4.63V. In all cases V
CC
acts as the master
supply (all resets are asserted when V
CC
goes below
its selected threshold). The V
CC
input also acts as the
device power supply.
The second block monitors both RESET IN2 and V
CC
. It
asserts a reset signal (LOW) whenever RESET IN2 is
below the 625mV threshold or V
CC
is below its reset
threshold. RESET2 remains asserted for a fixed 140ms
(min) or a user-adjustable time period after RESET IN2
rises above the 625mV reset threshold and RESET1 is
deasserted. Resets are guaranteed valid for V
CC
down
to 1V.
The timing diagram in Figure 2 shows the reset timing
characteristics of the MAX6391/MAX6392. As shown in
Figure 2, RESET1 deasserts 140ms (min) (t
RP1
) after
V
CC
exceeds the reset threshold. RESET2 deasserts
t
RP2
(140ms minimum or a user-adjustable timeout peri-
od) after RESET IN2 exceeds 625mV and RESET1 is
deasserted. When RESET IN2 drops below 625mV
while V
CC
is above the reset threshold, RESET2 asserts
within 10µs typ. RESET1 is unaffected when this hap-
pens. When V
CC
falls below V
TH1
, RESET2 always
asserts before RESET1 (t
RD2
< t
RD1
).
