ADF4153ABCPZ Datasheet ADF4153ABCPZ, ADF4153ABRUZ, ADF4153ABRUZ-RL7 | P19-P21

ADF4153A Data Sheet

Rev. A | Page 18 of 24

The programmable modulus is also very useful for multi-

standard applications. If a dual-mode phone requires PDC

and GSM 1800 standards, the programmable modulus is of

great benefit. PDC requires 25 kHz channel step resolution,

whereas GSM 1800 requires 200 kHz channel step resolution.

A 13 MHz reference signal can be fed directly to the PFD. The

modulus is programmed to 520 when in PDC mode (13 MHz/

520 = 25 kHz). The modulus is reprogrammed to 65 for GSM

1800 operation (13 MHz/65 = 200 kHz). It is important that the

PFD frequency remains constant (13 MHz). This lets the user

design one loop filter that can be used in both setups without

running into stability issues. It is the ratio of the RF frequency

to the PFD frequency that affects the loop design. By keeping

this relationship constant, the same loop filter can be used in

both applications.

FASTLOCK WITH SPURIOUS OPTIMIZATION

As mentioned in the Noise and Spur Mode section, the part

can be optimized for spurious performance. However, in fast-

locking applications, the loop bandwidth needs to be wide,

and therefore the filter does not provide much attenuation of

the spurs. The programmable charge pump can be used to get

around this issue. The filter is designed for a narrow-loop

bandwidth so that steady-state spurious specifications are met.

This is designed using the lowest charge pump current setting.

To implement fastlock during a frequency jump, the charge

pump current is set to the maximum setting for the duration of

the jump by asserting the fastlock bit in the N divider register.

This widens the loop bandwidth, which improves lock time. To

maintain loop stability while in wide bandwidth mode, the loop

filter needs to be modified. This is achieved by switching in a

resistor (R1A) in parallel with the damping resistor in the loop

filter (see Figure 21). MUXOUT needs to be set to the fastlock

switch to use the internal switch. For example, if the charge

pump current is increased by 16, the damping resistor, R1,

needs to be decreased by ¼ while in wide bandwidth mode.

ADF4153A

VCO

MUXOUT

R1A

11047-021

Figure 21. ADF4153A with Fastlock

The value of R1A is then chosen so that the total parallel

resistance of R1 and R1A equals 1/4 of R1 alone. This gives

an overall 4× increase in loop bandwidth, while maintaining

stability in wide bandwidth mode.

When the PLL has locked to the new frequency, the charge

pump is again programmed to the lowest charge pump current

setting by setting the fastlock bit to 0. The internal switch opens

and the damping resistor reverts to its original value. This

narrows the loop bandwidth to its original cutoff frequency

to allow better attenuation of the spurs than the wide-loop

bandwidth.

SPUR MECHANISMS

The following section describes the three different spur mechan-

isms that arise with a fractional-N synthesizer and how to

minimize them in the ADF4153A.

Fractional Spurs

The fractional interpolator in the ADF4153A is a third-order

Σ-Δ modulator (SDM) with a modulus (MOD) that is program-

mable to any integer value from 2 to 4095. In low spur mode

(dither enabled), the minimum allowed value of MOD is 50.

The SDM is clocked at the PFD reference rate (F

PFD

) that allows

PLL output frequencies to be synthesized at a channel step

resolution of F

PFD

/MOD.

In lowest noise mode and low noise and spur mode (dither off),

the quantization noise from the Σ-Δ modulator appears as frac-

tional spurs. The interval between spurs is F

PFD

/L, where L is the

repeat length of the code sequence in the digital Σ-Δ modulator.

For the third-order modulator used in the ADF4153A, the repeat

length depends on the value of MOD, as shown in Table 6.

Table 6. Fractional Spurs with Dither Off

Condition (Dither Off)

Repeat

Length

Spur Interval

If MOD is divisible by 2, but not 3 2 × MOD Channel step/2

If MOD is divisible by 3, but not 2 3 × MOD Channel step/3

If MOD is divisible by 6 6 × MOD Channel step/6

Otherwise MOD Channel step

In low spur mode (dither enabled), the repeat length is

extended to 2

cycles, regardless of the value of MOD, which

makes the quantization error spectrum look like broadband

noise. This can degrade the in-band phase noise at the PLL

output by as much as 10 dB. Therefore, for lowest noise, dither

off is a better choice, particularly when the final loop BW is low

enough to attenuate even the lowest frequency fractional spur.

Integer Boundary Spurs

Another mechanism for fractional spur creation is interactions

between the RF VCO frequency and the reference frequency.

When these frequencies are not integer related (which is the

point of a fractional-N synthesizer), spur sidebands appear on

the VCO output spectrum at an offset frequency that corresponds

to the beat note or difference frequency between an integer

multiple of the reference and the VCO frequency.

These spurs are attenuated by the loop filter and are more

noticeable on channels close to integer multiples of the

reference where the difference frequency can be inside the

loop bandwidth, therefore, the name integer boundary spurs.

Data Sheet ADF4153A

Rev. A | Page 19 of 24

Reference Spurs

Reference spurs are generally not a problem in fractional-N

synthesizers because the reference offset is far outside the

loop bandwidth. However, any reference feedthrough mechan-

ism that bypasses the loop can cause a problem. One such

mechanism is feedthrough of low levels of on-chip reference

switching noise out through the RF

pin back to the VCO,

resulting in reference spur levels as high as –90 dBc. Ensure that

in the PCB layout that the VCO is well separated from the input

reference to avoid a possible feed-through path on the board.

SPUR CONSISTENCY

When jumping from Frequency A to Frequency B and then

back again using some fractional-N synthesizers, the spur levels

often differ each time Frequency A is programmed. However,

in the ADF4153A, the spur levels on any particular channel are

always consistent.

PHASE RESYNC

The output of a fractional-N PLL can settle to any one of MOD

phase offsets with respect to the input reference, where MOD

is the fractional modulus. The phase resync feature in the

ADF4153A can be used to produce a consistent output phase

offset with respect to the input reference. This is necessary

in applications where the output phase and frequency are

important, such as digital beam-forming.

When phase resync is enabled, an internal timer generates sync

signals at intervals of t

SYNC

given by the following formula:

SYNC

= RESYNC × RESYNC_DELAY × t

PFD

where t

PFD

is the PFD reference period.

RESYNC is the decimal value programmed in Bits DB[15…12]

of Register R2 and can be any integer in the range of 1 to 15. If

RESYNC is programmed to its default value of all zeros, then

the phase resync feature is disabled.

If phase resync is enabled, then RESYNC_DELAY must be

programmed to a value that is an integer multiple of the value

of MOD. RESYNC_DELAY is the decimal value programmed

into the MOD bits (DB[13…2] of Register R1 when load

control (Bit DB23 of Register R1) = 1.

When a new frequency is programmed, the second next sync

pulse after the LE rising edge is used to resynchronize the output

phase to the reference. The t

SYNC

time should be programmed to

a value that is at least as long as the worst-case lock time. Doing

so guarantees that the phase resync occurs after the last cycle

slip in the PLL settling transient.

In the example shown in Figure 22, the PFD reference is

25 MHz and MOD = 125 for a 200 kHz channel spacing.

SYNC

is set to 400 µs by programming RESYNC = 10 and

RESYNC_DELAY = 1000.

PHASE

FREQUENCY

SYNC

(INTERNAL)

–100 0

100 200 1000

300 400 500 600 700 800

900

TIME (µs)

PLL SETTLES TO

CORRECT PHASE

AFTER RESYNC

LAST CYCLE SLIP

PLL SETTLES TO

INCORRECT PHASE

SYNC

11047-022

Figure 22. Phase Resync Example

FILTER DESIGN—ADIsimPLL

A filter design and analysis program is available to help the user

implement PLL design. Visit www.analog.com/pll for a free

download of the ADIsimPLL™ software. The software designs,

simulates, and analyzes the entire PLL frequency domain and

time domain response. Various passive and active filter

architectures are allowed.

INTERFACING

The ADF4153A has a simple SPI®-compatible serial interface

for writing to the device. CLK, DATA, and LE control the data

transfer. When latch enable (LE) is high, the 22 bits that are

clocked into the input register on each rising edge of SCLK are

transferred to the appropriate latch. See Figure 2 for the timing

diagram and Table 5 for the register truth table.

The maximum allowable serial clock rate is 20 MHz.

ADF4153A Data Sheet

Rev. A | Page 20 of 24

ADuC812 Interface

Figure 23 shows the interface between the ADF4153A and the

ADuC812 MicroConverter®. Because the ADuC812 is based on

an 8051 core, this interface can be used with any 8051-based

microcontroller. The MicroConverter is set up for SPI master

mode with CPHA = 0. To initiate the operation, the I/O port

driving LE is brought low. Each latch of the ADF4153A needs a

24-bit word, which is accomplished by writing three 8-bit bytes

from the MicroConverter to the device. After the third byte is

written, the LE input should be brought high to complete the

transfer.

ADuC812

ADF4153A

SCLOCK

CLK

DATA

MUXOUT

(LOCK DETECT)

MOSI

I/O PORTS

11047-023

Figure 23. ADuC812 to ADF4153A Interface

When operating in this mode, the maximum SCLOCK rate of

the ADuC812 is 4 MHz. This means that the maximum rate at

which the output frequency can be changed is 180 kHz.

ADSP-21xx Interface

Figure 24 shows the interface between the ADF4153A and the

ADSP-21xx digital signal processor. As discussed previously,

the ADF4153A needs a 24-bit serial word for each latch write.

The easiest way to accomplish this using the ADSP-21xx family

is to use the autobuffered transmit mode of operation with

alternate framing. This provides a means for transmitting an

entire block of serial data before an interrupt is generated.

Set up the word length for eight bits and use three memory

locations for each 24-bit word. To program each 24-bit latch,

store the three 8-bit bytes, enable the autobuffered mode, and

write to the transmit register of the DSP. This last operation

initiates the autobuffer transfer.

ADSP-21xx

ADF4153A

SCLK CLK

DATA

MUXOUT

(LOCK DETECT)

TFS

I/O FLAGS

11047-024

Figure 24. ADSP-21xx to ADF4153A Interface

PCB DESIGN GUIDELINES FOR CHIP SCALE

PACKAGE

The lands on the chip scale package (CP-20) are rectangular.

The printed circuit board (PCB) pad for these should be 0.1 mm

longer than the package land length and 0.05 mm wider than

the package land width. The land should be centered on the

pad. This ensures that the solder joint size is maximized.

The bottom of the chip scale package has a central thermal pad.

The thermal pad on the PCB should be at least as large as this

exposed pad. On the PCB, there should be a clearance of at least

0.25 mm between the thermal pad and the inner edges of the

pad pattern. This ensures that shorting is avoided.

Thermal vias can be used on the PCB thermal pad to improve

thermal performance of the package. If vias are used, they should

be incorporated in the thermal pad at 1.2 mm pitch grid. The

via diameter should be between 0.3 mm and 0.33 mm, and the

via barrel should be plated with one ounce of copper to plug the

via. The user should connect the PDB thermal pad to AGND.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P25

ADF4153ABCPZ

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Phase Locked Loops - PLL Fractional-N Freq Synthesizer

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