Data Sheet ADF4153A
Rev. A | Page 3 of 24
SPECIFICATIONS
AV
DD
= DV
DD
= SDV
DD
= 2.7 V to 3.3 V; V
P
= AV
DD
to 5.5 V; AGND = DGND = 0 V; T
A
= T
MIN
to T
MAX
, unless otherwise noted;
dBm referred to 50 Ω.
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
RF INPUT CHARACTERISTICS (3 V)
See
Figure 12 for an input circuit
RF Input Frequency (RF
IN
) 0.5 4 GHz −8 dBm minimum/0 dBm maximum
1 4 GHz −10 dBm minimum/0 dBm maximum
For lower frequencies, ensure slew rate
(SR) > 400 V/µs
REF
IN
CHARACTERISTICS
See
Figure 11 for an input circuit
REF
IN
Input Frequency 10 250 MHz For f < 10 MHz, use a dc-coupled,
CMOS-compatible square wave;
slew rate > 25 V/µs
REF
IN
Input Sensitivity 0.7 AV
DD
V p-p Biased at AV
DD
/2
1
REF
IN
Input Capacitance 10 pF
REF
IN
Input Current ±100 µA
Phase Detector Frequency 32 MHz
CHARGE PUMP
I
CP
Sink/Source
Programmable; see
Figure 19
High Value 5 mA With R
SET
= 4.7 kΩ
SET
Absolute Accuracy 2.5 % With R
SET
= 4.7 kΩ
R
SET
Range 3.0 10 kΩ
I
CP
Three-State Leakage Current 1 nA Sink and source current
Sink and Source Matching 2 % 0.5 V ≤ V
CP
≤ V
P
− 0.5 V
I
CP
vs. V
CP
2 % 0.5 V ≤ V
CP
≤ V
P
− 0.5 V
I
CP
vs. Temperature 2 % V
CP
= V
P
/2
LOGIC INPUTS
V
INH
, Input High Voltage 1.4 V
INL
I
INH
/I
INL
, Input Current ±1 µA
C
IN
, Input Capacitance 10 pF
LOGIC OUTPUTS
V
OH
, Output High Voltage 1.4 V Open-drain 1 kΩ pull-up to 1.8 V
V
OL
, Output Low Voltage 0.4 V I
OL
= 500 µA
POWER SUPPLIES
AV
DD
2.7 3.3 V
DD
VDD
DD
V
P
AV
DD
5.5 V
I
DD
20 24 mA
Low Power Sleep Mode 1 µA
NOISE CHARACTERISTICS
Normalized Phase Noise Floor (PN
SYNTH
)
2
−223 dBc/Hz PLL loop BW = 500 kHz
Normalized 1/f Noise (PN
1_f
)
3
−121 dBc/Hz Measured at 10 kHz offset, normalized to 1 GHz
Phase Noise Performance
4
@ VCO output
1750 MHz Output
5
−107 dBc/Hz @ 5 kHz offset, 25 MHz PFD frequency
1
AC coupling ensures AV
DD
/2 bias.
2
The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log(N) (where N is the N divider
value) and 10 log(F
PFD
). PN
SYNTH
= PN
TOT
− 10 log(F
PFD
) − 20 log(N).
3
The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency, F
RF
,
and at an offset frequency, f, is given by PN = P
1_f
+ 10 log(10 kHz/f) + 20 log(F
RF
/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in ADIsimPLL.
4
The phase noise is measured with the EV-ADF4153ASD1Z and the Rohde & Schwarz FSUP spectrum analyzer operating in phase noise mode.
5
f
REFIN
= 100 MHz; F
PFD
= 25 MHz; offset frequency = 5 kHz; RF
OUT
= 1750 MHz; N = 70; loop BW = 20 kHz; lowest noise mode.
