I
NTEGRATED
C
IRCUITS
D
IVISION
CPC5902
10 www.ixysic.com R03
3.2 Calculating Minimum Pull-Up Resistor Values
The minimum value of the pull-up resistor, R
PU
, on the
I
2
C bus is chosen based upon the expected V
DD
supply voltage range and the weakest load current
sinking device on the bus. Note: Systems that do not
need maximum bandwidth and busses with lower
capacitive loading can use a higher value for the
pull-up resistor to reduce power consumption.
3.2.1 Side A Pull-Up Resistor: R
PUA
The weakest I
2
C compliant device on the Side A bus,
with R
PUA
to V
DDA
, must be able to pull the Side A
inputs below 0.4V for outputs rated at 3mA or 0.6V for
outputs rated at 6mA when V
DDA
is at its maximum.
For example, if the weakest device is only guaranteed
to sink 3mA then the maximum allowed logic low
output voltage will be 0.4V. For designs with
V
DDA_max
= 3.6V, the minimum voltage across the
pull-up resistor is:
Minimum R
PUA
Voltage = 3.6 - 0.4 = 3.2V
For the I
2
C minimum current sink requirement of 3mA,
the minimum value of the pull-up resistor is easily
calculated as:
R
PUA_min
= 3.2V / 3mA = 1066.7
Chose a standard value resistor that will not violate
this minimum value over tolerance and temperature,
such as a 1.1k, 1% tolerance, 100ppm/C
temperature coefficient resistor.
If all the non-CPC5902 devices on the Side A bus are
Fast-mode compliant (400pF capacitive loading
capable) with the required 6mA current sink capability,
then the bus can be configured for Fast-mode.
Resistor selection for Fast-mode is similar to the
example given above but because the logic low output
level is greater (0.6V) then the voltage across the
pull-up resistor will be less. Calculation of the
compliant Fast-mode bus minimum pull-up resistor
value is given by:
R
PUA_min
= (3.6 - 0.6)V / 6mA = 500
The minimum E96 standard value 1% tolerance,
100ppm/C temperature coefficient resistor is 511.
3.2.2 Side B Pull-Up Resistor: R
PUB
Calculating the pull-up resistor for Side B is similar to
the process used for Side A but with some additional
considerations.
Before proceeding, it must be pointed out that Side B
of the CPC5902 is Fast-mode compliant with
V
DDB
4.5V. This means the CPC5902 Side B
outputs are 6mA capable allowing bus operation of
400kb/s with up to 400pF of capacitive loading. For
V
DDB
supply levels below 4.5V the CPC5902 outputs
are only rated for 3mA but can be operated at
Fast-mode speeds of 400kb/s whenever the bus
capacitive loading C
LOAD
200pF. Greater capacitive
loading of the Side B bus limits the CPC5902 to data
rates of 100kb/s.
First, it must be determined if the Side B bus will be
configured for 3mA or 6mA operation. This is done by
evaluating the external (non-CPC5602) devices on the
Side B bus and the operational capabilities of the
CPC5902. There are three possibilities:
1) One or more of the external devices is limited to
3mA of output current sink.
2) All of the external devices are rated at 6mA of
output current sink and the Side B minimum supply
voltage V
DDB
4.5V.
3) All of the external devices are rated at 6mA of
output current sink and the Side B minimum supply
voltage V
DDB
4.5V.
For conditions 1 and 2 above the bus must be
configured for 3mA. Condition 3 is the only situation
where the bus can be configured for 6mA, a
Fast-mode requirement when capacitive bus loading is
an issue.
Second, it is necessary to configure the Side B bus to
be compatible with the CPC5902’s lower logic low
input threshold:
V
ILB
= 0.2 • V
DDB
- 60mV
As discussed earlier, this lower input threshold
requirement is to ensure the CPC5902 can drive a
logic low output that is recognized by the other I
2
C
devices on the bus, but will not accept it’s own logic
low output. This prevents latching of the CPC5902.
Additionally, this implies there can be no more than
one limited drive (Side B) CPC5902 interface on the
Side B bus, and that all other devices on the Side B
bus must have V
IL
=0.3• V
DDB
logic low input
thresholds. Because the CPC5902 Side A inputs are
compatible with this requirement, any number of
