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AD7628KNZ

P1-P3P4-P6P7-P9
AD7628
–3–
REV. A
ABSOLUTE MAXIMUM RATINGS
(T
A
= +25°C unless otherwise noted)
V
DD
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, +17 V
V
DD
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, +17 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . V
DD
+ 0.3 V
DGND to AGND . . . . . . . . . . . . . . . . . . . . . . . . V
DD
+ 0.3 V
Digital Input Voltage to DGND . . . . . . –0.3 V, V
DD
+ 0.3 V
V
PIN2
, V
PIN20
to AGND . . . . . . . . . . . . . . –0.3 V, V
DD
+ 0.3 V
V
REF
A, V
REF
B to AGND . . . . . . . . . . . . . . . . . . . . . . . ±25 V
V
RFB
A, V
RFB
B to AGND . . . . . . . . . . . . . . . . . . . . . . . ±25 V
Power Dissipation (Any Package) to +75°C . . . . . . . . 450 mW
Derates above +75°C by . . . . . . . . . . . . . . . . . . . 6 mW/°C
Operating Temperature Range
Commercial (K) Grades . . . . . . . . . . . . . . . –40°C to +85°C
Industrial (B) Grades . . . . . . . . . . . . . . . . . –40°C to +85°C
Extended (T) Grades . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C
ORDERING GUIDE
Temperature Relative Gain Package
Model
1
Range Accuracy Error Option
2
AD7628KN –40°C to +85°C ±1/2 LSB ±2 LSB N-20
AD7628KP –40°C to +85°C ±1/2 LSB ±2 LSB P-20A
AD7628KR –40°C to +85°C ±1/2 LSB ±2 LSB R-20
AD7628BQ –40°C to +85°C ±1/2 LSB ±2 LSB Q-20
AD7628TQ –55°C to +125°C ±1/2 LSB ±2 LSB Q-20
AD7628TE –55°C to +125°C ±1/2 LSB ±2 LSB E-20A
NOTES
1
To order MIL-STD-883, Class B process parts, add /883B to part number.
Contact your local sales office for military data sheet.
2
E = Leadless Ceramic Chip Carrier; N = Plastic DIP; P = Plastic Leaded Chip
Carrier; Q = Cerdip; R = SOIC.
WARNING!
ESD SENSITIVE DEVICE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7628 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
TERMINOLOGY
Relative Accuracy:
Relative accuracy or endpoint nonlinearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after ad-
justing for zero and full-scale, and is normally expressed in
LSBs or as a percentage of full-scale reading.
Differential Nonlinearity:
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB max over
the operating temperature range ensures monotonicity.
Gain Error:
Gain error is a measure of the output error between an ideal
DAC and the actual device output. It is measured with all 1s in
the DAC latches after offset error has been adjusted out. Gain
error of both DACs is adjustable to zero with external resistance.
Output Capacitance:
Capacitance from OUT A or OUT B to AGND.
Digital-to-Analog Glitch Impulse:
The amount of charge injected from the digital inputs to the
analog output when the inputs change state. This is normally
specified as the area of the glitch in either pA-secs or nV-secs,
depending upon whether the glitch is measured as a current or
voltage signal. Glitch impulse is measured with V
REF
A, V
REF
B
= AGND.
Channel-to-Channel Isolation:
The proportion of input signal from one DAC’s reference input
that appears at the output of the other DAC, expressed as a
ratio in dB.
Digital Crosstalk:
The glitch energy transferred to the output of one converter due
to a change in digital input code to the other converter. Speci-
fied in nV secs.
PIN CONFIGURATIONS
DIP, SOIC
AGND
OUT A
OUT B
RFB B
DGND
DAC A/DAC B
(MSB) DB7
WR
CS
DB0 (LSB)
RFB A
V
REF
A
V
REF
B
V
DD
DB6 DB1
DB5
DB2
DB4
DB3
1
2
20
19
5
6
7
16
15
14
3
4
18
17
813
912
10 11
TOP VIEW
(Not to Scale)
AD7628
LCCC
V
REF
A
DGND
DB6
DAC A /DAC B
DB7 (MSB)
OUT A
RFB B
AGND
OUT B
DB5
DB4
DB1
DB3
DB2
V
REF
B
V
DD
DB0 (LSB)
WR
CS
1931220
4
5
8
6
7
12 1391110
18
17
14
16
15
TOP VIEW
(Not to Scale)
AD7628
RFB A
PLCC
V
REF
A
DGND
DB6
DAC A/DAC B
DB7 (MSB)
RFB A
OUT A
RFB B
AGND
OUT B
DB5
DB4
DB1
DB3
DB2
V
REF
B
V
DD
DB0 (LSB)
WR
CS
193
1
2 20
4
5
8
6
7
12 139
11
10
18
17
14
16
15
TOP VIEW
(Not to Scale)
AD7628
AD7628
–4–
REV. A
INTERFACE LOGIC INFORMATION
DAC Selection
Both DAC latches share a common 8-bit input port. The con-
trol input
DAC A/DAC B selects which DAC can accept data
from the input port.
Mode Selection
Inputs CS and WR control the operating mode of the selected
DAC. See Mode Selection Table below.
Write Mode
When CS and WR are both low, the selected DAC is in the write
mode. The input data latches of the selected DAC are transpar-
ent and its analog output responds to activity on DB0–DB7.
Hold Mode
The selected DAC latch retains the data that was present on
DB0–DB7 just prior to
CS or WR assuming a high state. Both
analog outputs remain at the values corresponding to the data in
their respective latches.
Mode Selection Table
DAC A/
DAC B CS WR DAC A DAC B
L L L WRITE HOLD
H L L HOLD WRITE
X H X HOLD HOLD
X X H HOLD HOLD
L = Low State, H = High State, X = Don’t Care
WRITE CYCLE TIMING DIAGRAM
CIRCUIT INFORMATION—D/A SECTION
The AD7628 contains two identical 8-bit multiplying D/A con-
verters, DAC A and DAC B. Each DAC consists of a highly
stable thin film R-2R ladder and eight N-channel current steering
switches. A simplified D/A circuit for DAC A is shown in Figure
1. An inverted R-2R ladder structure is used; that is, binary
Figure 1. Simplified Functional Circuit for DAC A
weighted currents are switched between the DAC output and
AGND, thus maintaining fixed currents in each ladder leg inde-
pendent of switch state.
EQUIVALENT CIRCUIT ANALYSIS
Figure 2 shows an approximate equivalent circuit for one of
the AD7628’s D/A converters, in this case DAC A. A similar
equivalent circuit can be drawn for DAC B. Note that AGND
(Pin 1) is common for both DAC A and DAC B.
The current source I
LEAKAGE
is composed of surface and junc-
tion leakages and, as with most semiconductor devices, approxi-
mately doubles every 10°C. The resistor Ro, as shown in Fig-
ure 2, is the equivalent output resistance of the device, which
varies with input code (excluding all 0s code) from 0.8R to 2R.
R is typically 11 kΩ. C
OUT
is the capacitance due to the N-channel
switches and varies from about 50 pF to 120 pF, depending on
the digital input. g(V
REF
A, N) is the Thevenin equivalent volt-
age generator due to the reference input voltage V
REF
A and the
transfer function of the R-2R ladder.
For further information on CMOS multiplying D/A converters,
refer to “CMOS DAC Application Guide, 2ND Edition” avail-
able from Analog Devices, Publication Number G872a–15–4/86.
Figure 2. Equivalent Analog Output Circuit of DAC A
CIRCUIT INFORMATION–DIGITAL SECTION
The input buffers are simple CMOS level-shifters designed so
that when the AD7628 is operated with V
DD
from 10.8 V to
15.75 V, the buffer converts TTL input levels (2.4 V and 0.8 V)
into CMOS logic levels. When V
IN
is in the region of 1.0 volt to
2.0 volts, the input buffers operate in their linear region and
pass a quiescent current (see Figure 3). To minimize power sup-
ply currents, it is recommended that the digital input voltages be as
close to the supply rails (V
DD
and DGND) as practicably possible.
The AD7628 may be operated with any supply voltage in the
range 10.8 ≤ V
DD
≤ 15.75 volts.
Figure 3. Typical Plot of Supply Current, I
DD
vs. Logic
Input Voltage V
IN
to V
DD
= +15 V
AD7628
–5–
REV. A
Table I. Unipolar Binary Code Table
DAC Latch Contents Analog Output
MSB LSB (DAC A or DAC B)
1 1 1 1 1 1 1 1
–V
IN
255
256
1 0 0 0 0 0 0 1
–V
IN
129
256
1 0 0 0 0 0 0 0
–V
IN
128
256
= –
V
IN
2
0 1 1 1 1 1 1 1
–V
IN
127
256
0 0 0 0 0 0 0 1
–V
IN
1
256
0 0 0 0 0 0 0 0
–V
IN
0
256
= 0
NOTE: 1 LSB = (2
–8
)(V
IN
) =
1
256
V
IN
()
Figure 4. Dual DAC Unipolar Binary Operation (2 Quadrant Multiplication). See Table I.
Figure 5. Dual DAC Bipolar Operation (4 Quadrant Multiplication). See Table II.
Table II. Bipolar (Offset Binary) Code Table
DAC Latch Contents Analog Output
MSB LSB (DAC A or DAC B)
1 1 1 1 1 1 1 1
+V
IN
127
128
1 0 0 0 0 0 0 1
+V
IN
1
128
1 0 0 0 0 0 0 0 0
0 1 1 1 1 1 1 1
–V
IN
1
128
0 0 0 0 0 0 0 1
–V
IN
127
128
0 0 0 0 0 0 0 0
–V
IN
128
128
NOTE: 1 LSB = (2
–7
)(V
IN
) =
1
128
V
IN
()
Table III. Recommended Trim Resistor Values
Trim
Resistor K/B/T
R1; R3 500
R2; R4 150
P1-P3P4-P6P7-P9

AD7628KNZ

Mfr. #:
Buy AD7628KNZ
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC CMOS Dual 8-Bit Buffered Multiplying
Lifecycle:
New from this manufacturer.
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