7
Table 7. Switching Specications
Unless otherwise noted, T
A
= –40°C to +105°C.
Parameter Sym Device Min Typ
[1]
Max Units Test Conditions/Notes Fig.
V
CC
= 4.5 V
Propagation Delay
Time to Logic Low
at Output
t
PHL
ACPL-K370 3.7 7.5
PsR
L
= 4.7 k:, C
L
= 30 pF; Note 2
10
ACPL-K376 6.2 12.5
Ps
ACPL-K370 3.7 7.5
PsR
L
= 1.8 k:, C
L
= 15 pF; Note 2
ACPL-K376 6.3 12.5
Ps
Propagation Delay
Time to Logic High
at Output
t
PLH
ACPL-K370 13.8 70
PsR
L
= 4.7 k:, C
L
= 30 pF; Note 3
10
ACPL-K376 13.3 70
Ps
ACPL-K370 8.5 45
PsR
L
= 1.8 k:, C
L
= 15 pF; Note 3
ACPL-K376 6.4 45
Ps
Output Rise Time
(10-90%)
t
R
ACPL-K370 25
PsR
L
= 4.7 k:, C
L
= 30 pF
11
ACPL-K376 24
Ps
Output Fall Time
(90-10%)
t
F
ACPL-K370 0.3
PsR
L
= 4.7 k:, C
L
= 30 pF
11
ACPL-K376 0.4
Ps
V
CC
= 3.3 V
Propagation Delay
Time to Logic Low
at Output
t
PHL
ACPL-K370 4 7.5
PsR
L
= 4.7 k:, C
L
= 30 pF; Note 2
ACPL-K376 6.8 12.5
Ps
ACPL-K370 4 7.5
PsR
L
= 1.8 k:, C
L
= 15 pF; Note 2
ACPL-K376 6.9 12.5
Ps
Propagation Delay
Time to Logic High
at Output
t
PLH
ACPL-K370 19 90
PsR
L
= 4.7 k:, C
L
= 30 pF; Note 3
ACPL-K376 18.5 90
Ps
ACPL-K370 12.8 70
PsR
L
= 1.8 k:, C
L
= 15 pF; Note 3
ACPL-K376 12.5 70
Ps
Output Rise Time
(10-90%)
t
R
ACPL-K370 27
PsR
L
= 4.7 k:, C
L
= 30 pF
ACPL-K376 26
Ps
Output Fall Time
(90-10%)
t
F
ACPL-K370 0.3
PsR
L
= 4.7 k:, C
L
= 30 pF
ACPL-K376 0.5
Ps
V
CC
= 3 V to 5.5 V
Common Mode
Transient Immunity
at Logic High Output
|CM
H
|10
kV/PsI
IN
= 0 mA, R
L
= 4.7 k:, V
O,MIN
= 2 V,
V
CM
= 1500 V; Notes 4, 5
Common Mode
Transient Immunity
at Logic Low Output
|CM
L
| ACPL-K370 1
kV/PsI
IN
= 3.11 mA, R
L
= 4.7 k:, V
O,MAX
=
0.8 V, V
CM
= 500 V; Notes 4, 5
ACPL-K376 1
kV/PsI
IN
= 1.56 mA, R
L
= 4.7 k:, V
O,MAX
=
0.8 V, V
CM
= 500 V; Notes 4, 5
Notes:
1. All typical values are at T
A
= 25°C unless otherwise stated.
2. The t
PHL
propagation delay is measured from the 2.5 V level of the leading edge of a 5.0 V input pulse (1 Ps rise time) to the 1.5 V level on the leading
edge of the output pulse. C
L
includes probe and stray wiring capacitance.
3. The t
PLH
propagation delay is measured from the 2.5 V level of the trailing edge of a 5.0 V input pulse (1 Ps fall time) to the 1.5 V level on the trailing
edge of the output pulse. C
L
includes probe and stray wiring capacitance.
4. Common mode transient immunity with a logic “High” level is the maximum tolerable (positive) dV
CM
/dt on the leading edge of the common
mode pulse, V
CM
, to insure that the output will remain in a logic “High” state (i.e., V
O
> 2.0 V). Common mode transient immunity in logic “Low” level
is the maximum tolerable (negative) dV
CM
/dt on the trailing edge of the common mode pulse signal, V
CM
, to insure that the output will remain in
a logic “Low” state (i.e., V
O
< 0.8 V).
5. In applications where dV
CM
/dt may exceed 50 kV / μs (such as when a static discharge occurs), a series resistor, R
CC
, should be included to protect
the detector IC from destructive high surge currents. The recommended value for R
CC
is 240 : per volt of allowable drop in V
CC
(between pin 8 and
V
CC
) with a minimum value of 240 :.
