IDT
TM
/ICS
TM
Ultra Mobile PC Clock for Industrial Temperature Range 1451—01/20/09
ICS9UMS9633BI
ULTRA MOBILE PC CLOCK FOR INDUSTRIAL TEMPERATURE RANGE
14
Advance Information
Byte 2 Output Enable Register
Bit(s) Pin # Name Description Type 0 1 Default
7 CPU0 Enable
This bit controls whether the CPU[0] output buffer
is enabled or not.
RW 0 = Disabled 1 = Enabled 1
6 CPU1 Enable
This bit controls whether the CPU[1] output buffer
is enabled or not.
RW 0 = Disabled 1 = Enabled 1
5 CPU2 Enable
This bit controls whether the CPU[2] output buffer
is enabled or not.
RW 0 = Disabled 1 = Enabled 1
4 SRC0 Enable
This bit controls whether the SRC[0] output buffer
is enabled or not.
RW 0 = Disabled 1 = Enabled 1
3 SRC1 Enable
This bit controls whether the SRC[1] output buffer
is enabled or not.
RW 0 = Disabled 1 = Enabled 1
2 SRC2 Enable
This bit controls whether the SRC[2] output buffer
is enabled or not.
RW 0 = Disabled 1 = Enabled 1
1 DOT Enable
This bit controls whether the DOT output buffer is
enabled or not.
RW 0 = Disabled 1 = Enabled 1
0 LCD100 Enable
This bit controls whether the LCD output buffer is
enabled or not.
RW 0 = Disabled 1 = Enabled 1
Byte 3 Output Control Register
Bit(s) Pin # Name Description Type 0 1 Default
7 0
6 0
5 REF Enable
This bit controls whether the REF output buffer is
enabled or not.
RW 0 = Disabled 1 = Enabled 1
4
3
2 CPU0 Stop Enable
This bit controls whether the CPU[0] output buffer
is free-running or stoppable. If it is set to stoppable
the CPU[0] output buffer will be disabled with the
assertion of CPU_STP#.
RW Free Running Stoppable 0
1 CPU1 Stop Enable
This bit controls whether the CPU[1] output buffer
is free-running or stoppable. If it is set to stoppable
the CPU[1] output buffer will be disabled with the
assertion of CPU_STP#.
RW Free Running Stoppable 0
0 CPU2 Stop Enable
This bit controls whether the CPU[2] output buffer
is free-running or stoppable. If it is set to stoppable
the CPU[2] output buffer will be disabled with the
assertion of CPU_STP#.
RW Free Running Stoppable 0
10REF Slew
00 = Slow Edge Rate
01 = Medium Edge Rate
10 = Fast Edge Rate
11 = Reserved
RWThese bits control the edge rate of the REF clock.
Reserved
Reserved