4
Figure 3. Recommended Decoupling and Termination Circuits
o
V
EE
R
X
o
V
CC
R
X
o
SD
o
RD-
o
RD+
Z = 50 Ω
Z = 50 Ω
TERMINATE AT
TRANSCEIVER INPUTS
Z = 50 Ω
Z = 50 Ω
10 9 8 7 6
SD
LVPECL
V
CC
(+3.3 V)
TERMINATE AT
DEVICE INPUTS
LVPECL
V
CC
(+3.3 V)
PHY DEVICE
TD+
TD-
RD+
RD-
V
CC
(+3.3 V)
Z = 50 Ω
1 2 3 4 5
TD-
o
TD+
o
N/C
o
V
EE
T
X
o
V
CC
T
X
o
1 μH
C2
1 μH
C1
C3
10 μF
V
CC
(+3.3 V)
T
X
R
X
Notes:
C1 = C2 = C3 = 10 nF or 100 nF
* Loading of R1 is optional.
100 Ω
100 Ω
130 Ω
130 Ω
130 Ω
130 Ω
LVTTL
R1*
4.7KΩ
Recommended Handling Precautions
Avago recommends that normal static precautions be
taken in the handling and assembly of these transceivers
to prevent damage which may be induced by electrostatic
discharge (ESD).
The HFBR-5963xxZ series of transceivers meet MIL-STD-
883C Method 3015.4 Class 2 products.
Care should be used to avoid shorting the receiver data or
signal detect outputs directly to ground without proper
current limiting impedance.
Solder and Wash Process Compatibility
The transceivers are delivered with protective process
plugs inserted into the LC receptacle.
This process plug protects the optical subassemblies
during wave solder and aqueous wash processing and
acts as a dust cover during shipping.
These transceivers are compatible with either industry
standard wave or hand solder processes.
Shipping Container
The transceiver is packaged in a shipping container
designed to protect it from mechanical and ESD damage
during shipment or storage.
Board Layout - Decoupling Circuit, Ground Planes and
Termination Circuits
It is important to take care in the layout of your circuit
board to achieve optimum performance from these trans-
ceivers. Figure 3 provides a good example of a schematic
for a power supply decoupling circuit that works well
with these parts. It is further recommended that a con-
tiguous ground plane be provided in the circuit board
directly under the transceiver to provide a low inductance
ground for signal return current. This recommendation
is in keeping with good high frequency board layout
practices. Figures 3 and 4 show two recommended ter-
mination schemes.
5
Figure 4. Alternative Termination Circuits
o V
EE
R
X
o V
CC
R
X
o SD
o RD-
o RD+
Z = 50 Ω
130 Ω
V
CC
(+3.3 V)
10 nF
Z = 50 Ω
130 Ω
82 Ω 82 Ω
TERMINATE AT
TRANSCEIVER INPUTS
Z = 50 Ω
Z = 50 Ω
10 9 8 7 6
SD
LVPECL
V
CC
(+3.3 V)
TERMINATE AT DEVICE INPUTS
LVPECL
V
CC
(+3.3 V)
PHY DEVICE
TD+
TD-
RD+
RD-
Z = 50 Ω
1 2 3 4 5
TD- o
TD+ o
N/C o
V
EE
T
X
o
V
CC
T
X
o
1 μH
C2
1 μH
C1
C3
10 μF
V
CC
(+3.3 V)
T
X
R
X
Note:
C1 = C2 = C3 = 10 nF or 100 nF
* Loading R1 is optional.
10 nF
130 Ω
82 Ω
V
CC
(+3.3 V)
130 Ω
82 Ω
V
CC
(+3.3 V)
R1*
4.7KΩ
LVTTL
Board Layout - Hole Pattern
The Avago transceiver complies with the circuit board
“Common Transceiver Footprint hole pattern de ned in
the original multisource announcement which de ned the
2 x 5 package style. This drawing is reproduced in Figure
6 with the addition of ANSI Y14.5M compliant dimension-
ing to be used as a guide in the mechanical layout of your
circuit board. Figure 6 illustrates the recommended panel
opening and the position of the circuit board with respect
to this panel.
Regulatory Compliance
These transceiver products are intended to enable
commercial system designers to develop equipment
that complies with the various international regula-
tions governing certi cation of Information Technology
Equipment. See the Regulatory Compliance Table for
details. Additional information is available from your
Avago sales representative.
6
ALL DIMENSIONS IN MILIMETERS(INCHES)
Figure 5. Package Outline Drawing

HFBR-5963ALZ

Mfr. #:
Manufacturer:
Broadcom / Avago
Description:
Fiber Optic Transmitters, Receivers, Transceivers OC3/FE 2X5 LC SD LVT TL EX TP ROHS
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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