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LTC1874EGN#TRPBF

P1-P3P4-P6P7-P9P10-P12
10
LTC1874
Figure 3. Line Regulation of V
REF
and V
ITH
INPUT VOLTAGE (V)
2.0
NORMALIZED VOLTAGE (%)
105
100
95
90
85
80
75
2.2 2.4 2.6 2.8
1874 F03
3.0
V
REF
V
ITH
Figure 4. Setting Output Voltage
Low Supply Operation
Although the controller can function down to approxi-
mately 2.0V, the maximum allowable output current is
reduced when V
IN
decreases below 3V. Figure 3 shows the
amount of change as the supply is reduced down to 2V.
Also shown in Figure 3 is the effect of V
IN
on V
REF
as V
IN
goes below 2.3V.
Setting Output Voltage
The controller develops a 0.8V reference voltage between
the feedback (V
FB
) terminal and ground (see Figure 4). By
selecting resistor R1, a constant current is caused to flow
through R1 and R2 to set the overall output voltage. The
regulated output voltage is determined by:
VV
R
R
OUT
=+
08 1
2
1
.
For most applications, an 80k resistor is suggested for R1.
To prevent stray pickup, locate resistors R1 and R2 close
to the LTC1874.
Foldback Current Limiting
As described in the Output Diode Selection, the worst-
case dissipation occurs with a short-circuited output
when the diode conducts the current limit value almost
continuously. To prevent excessive heating in the diode,
foldback current limiting can be added to reduce the
current in proportion to the severity of the fault.
Foldback current limiting is implemented by adding di-
odes D
FB1
and D
FB2
between the output and the I
TH
/RUN
pin as shown in Figure 5. In a hard short (V
OUT
= 0V), the
current will be reduced to approximately 50% of the
maximum output current.
4
V
FB1
3
GND1
V
OUT
1/2 LTC1874
R1
1874F04
R2
Figure 5. Foldback Current Limiting
V
FB1
GND1
I
TH
/RUN1
V
OUT
1/2 LTC1874
R1
1874 F05
R2
4
3
13
D
FB1
D
FB2
+
APPLICATIO S I FOR ATIO
WUUU
11
LTC1874
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC1874. These items are illustrated graphically for a
single controller in the layout diagram in Figure 6. Check
the following in your layout:
1. Is the Schottky diode closely connected between power
ground (PGND) and the drain of the external MOSFET?
2. Does the (+) plate of C
IN
connect to the sense resistor
as closely as possible? This capacitor provides AC
current to the MOSFET.
3. Is the input decoupling capacitor (0.1µF) connected
closely between V
IN
and signal ground (GND)?
4. Connect the end of R
SENSE
as close to V
IN
as possible.
The V
IN
pin is the SENSE
+
of the current comparator.
5. Is the trace from SENSE
–
to the SENSE resistor kept
short? Does the trace connect close to R
SENSE
?
6. Keep the switching node PGATE away from sensitive
small signal nodes.
7. Does the V
FB
pin connect directly to the feedback
resistors? The resistive divider R1 and R2 must be
connected between the (+) plate of C
OUT
and signal
ground.
8. PV
IN
must connect to V
IN
and PGND must connect to
GND. Isolate high current power paths from signal
power and signal ground where possible in the layout.
An unbroken ground plane is recommended.
Figure 6. LTC1874 Layout Diagram (See PC Board Layout Checklist)
V
IN
SENSE
–
GND
V
FB
16
15
14
13
1
2
3
4
PV
IN
PGATE
PGND
I
TH
/RUN
1/2 LTC1874
0.1µF
R
SENSE
C
IN
C
OUT
V
OUT
V
IN
D1
L1
M1
SW
R
ITH
C
ITH
1874 F06
+
R2
BOLD LINES INDICATE HIGH CURRENT PATHS
R1
+
APPLICATIO S I FOR ATIO
WUUU
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
12
LTC1874
1874f LT/TP 0201 4K • PRINTED IN USA
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No R
SENSE
is a trademark of Linear Technology Corporation.
LINEAR TECHNOLOGY CORPORATION 2000
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear-tech.com
LTC1874 2.5V–8.5V Input to 3.3V/1A and 1.8V/1A Dual Converter
GN16 (SSOP) 1098
* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
0.016 – 0.050
(0.406 – 1.270)
0.015
± 0.004
(0.38 ± 0.10)
× 45°
0° – 8° TYP
0.007 – 0.0098
(0.178 – 0.249)
0.053 – 0.068
(1.351 – 1.727)
0.008 – 0.012
(0.203 – 0.305)
0.004 – 0.0098
(0.102 – 0.249)
0.0250
(0.635)
BSC
12
3
4
5
6
7
8
0.229 – 0.244
(5.817 – 6.198)
0.150 – 0.157**
(3.810 – 3.988)
16
15
14
13
0.189 – 0.196*
(4.801 – 4.978)
12 11 10
9
0.009
(0.229)
REF
Dimensions in inches (millimeters) unless otherwise noted.
GN Package
16-Lead Plastic SSOP (Narrow 0.150)
(LTC DWG # 05-08-1641)
TYPICAL APPLICATIO
U
U
PACKAGE DESCRIPTIO
V
IN1
SENSE1
–
GND1
V
FB1
I
TH
/RUN1
PGND1
PGATE1
PV
IN1
8
7
6
5
12
11
10
9
1
2
3
4
13
14
15
16
PV
IN2
PGATE2
PGND2
I
TH
/RUN2
V
FB2
GND2
SENSE2
–
V
IN2
LTC1874
10k
220pF
M2
D2
C2
47µF
6V
R2
0.082Ω
L2
4.7µH
220pF
10k
R1
0.03Ω
80.6k
1874 TA02
100k
V
OUT2
1.8V
1A
+
80.6k
249k
C1
47µF
×2
C1, C2: SANYO POSCAP 6TPA47M
C
IN
: TAIYO YUDEN CERAMIC
EMK325BJ106MNT (×2)
D1: 15MQ040N
D2: MBRM120
L1: BH-ELECTRONICS BH511-1012
L2: COILTRONICS UP2B-4R7
M1, M2: Si3443DV
R1, R2: DALE 0.25W
L1
+
C
IN
10µF
16V
×2
V
IN
2.5V TO 8.5V
D1
L1A
M1
V
OUT1
3.3V
1A
•
•
P1-P3P4-P6P7-P9P10-P12

LTC1874EGN#TRPBF

Mfr. #:
Buy LTC1874EGN#TRPBF
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 2x Const Freq C Mode Buck DC/DC Cntr
Lifecycle:
New from this manufacturer.
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