LTC4241
7
sn4241 4241f
12V
IN
(Pin 1): 12V Supply Input. This pin powers the
primary controller internal circuitry. A 0.5 switch is
connected between 12V
IN
and 12V
OUT
with a foldback
current limit. An undervoltage lockout circuit prevents the
switches from turning on while the 12V
IN
pin voltage is
less than 9V.
V
EEIN
(Pin 2): –12V Supply Input. A 1.2 switch is
connected between V
EEIN
and V
EEOUT
with a foldback
current limit.
3V
OUT
(Pin 3): 3.3V Output Monitor. Used to monitor the
3.3V output supply voltage. The PWRGD signal cannot go
low until the 3V
OUT
pin exceeds 2.9V.
TIMER (Pin 4): Current Limit Fault Timer Input. Connect a
capacitor from TIMER to ground. With the primary con-
troller turned off (ON = GND) or the internal circuit breaker
tripped due to a PCI supply fault (FAULT = low), the TIMER
pin is internally held at ground. When the primary control-
ler is turned on, a 22µA pull-up current source is con-
nected to TIMER. Current limit faults from the PCI supplies
will be ignored until the voltage at the TIMER pin rises to
within 0.9V of 12V
IN
.
ON (Pin 5): On Control Input. A rising edge turns on the
external N-channel FETs for 3.3V and 5V PCI supplies, the
internal 12V and –12V switches and a falling edge turns it
off. If the ON pin is cycled low then high following the trip
of the circuit breaker due to a PCI supply fault, the circuit
breaker is reset.
FAULT (Pin 6): Fault Output. Open drain logic output used
by both the primary and auxiliary controller to indicate an
overcurrent fault condition. When any of the PCI and 3.3V
auxiliary supplies are in current limit fault, the controller
detecting the fault (primary or auxiliary) will be latched off
and the FAULT pin will be pulled low. Current limit faults
from the PCI supplies are ignored while the voltage at the
TIMER pin is less than (12V
IN
– 0.9V). The current limit
fault detected by the primary controller will not cause the
auxiliary controller to latch off and vice versa.
PWRGD (Pin 7): Power Good Output. Open drain logic
output used by the primary controller to indicate the
voltage status of the PCI supplies. PWRGD remains low
while V
12VOUT
11.1V, V
3VOUT
2.9V, V
5VOUT
4.65V,
V
VEEOUT
–10.5V. When one of the supplies falls below its
UU
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PI FU CTIO S
power good threshold voltage, PWRGD will go high after
a 15µs deglitching time. The switches will not be turned off
when PWRGD goes high.
GND (Pin 8): Chip Ground
AUXGATE (Pin 9): High Side Gate Drive for the 3.3V
Auxiliary External N-channel MOSFET. An internal charge
pump generates at least 8V of gate drive from a 3.3V
auxiliary supply. A zener clamps AUXGATE approximately
12V above the supply voltage at AUXIN. The rise time at
AUXGATE is set by an external AUXGATE capacitor con-
nected to ground and an internal 10µA current source
provided by the charge pump. If the circuit breaker trips or
the auxiliary supply voltage hits the undervoltage lockout
threshold, a 50mA current sink rapidly pulls AUXGATE
low.
AUXSENSE (Pin 10): 3.3V Auxiliary Circuit Breaker Cur-
rent Sense Input. The load current is monitored by a sense
resistor connected between AUXIN and AUXSENSE. The
circuit breaker trips if the voltage across the sense resistor
exceeds 50mV and the AUXGATE pin voltage will be turned
off.
AUXIN (Pin 11): 3.3V Auxiliary Supply Input. This pin
powers the auxiliary controller internal circuitry. An
undervoltage lockout circuit disables the AUXGATE pin
until the supply voltage at AUXIN is greater than 2.6V.
AUXGATE is held at ground potential until the undervoltage
lockout deactivates. If no 3.3V auxiliary supply is available,
tie AUXIN to ground.
AUXON (Pin 12): ON Control Input for Auxiliary Supply. A
rising edge turns on the external N-channel FET for 3.3V
auxiliary supply and a falling edge turns it off. If the AUXON
pin is cycled low then high following the trip of the circuit
breaker due to a 3.3V auxiliary supply fault, the circuit
breaker is reset.
3V
IN
(Pin 13): 3.3V Supply Sense Input. An undervoltage
lockout circuit prevents the switches from turning on
when the voltage at the 3V
IN
pin is less than 2.5V. If no 3.3V
input supply is available, tie 3V
IN
to the 5V
IN
pin.
3V
SENSE
(Pin 14): 3.3V Current Limit Set Pin. With a sense
resistor placed in the supply path between 3V
IN
and
3V
SENSE
, the GATE pin voltage will be adjusted to maintain
LTC4241
8
sn4241 4241f
UU
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PI FU CTIO S
a constant voltage across the sense resistor and a
constant current through the switch. A foldback feature
makes the current limit decrease as the voltage at the
3V
OUT
pin approaches ground. To disable the current limit,
3V
SENSE
and 3V
IN
can be shorted together.
GATE (Pin 15): High Side Gate Drive for the 3.3V and 5V
PCI Supplies External N-channel MOSFETs. Requires an
external series RC network for the current limit loop
compensation and setting the minimum ramp-up rate.
During power-up, the slope of the voltage rise at the GATE
is set by the internal 60µA pull up current source and the
external GATE capacitor connected to ground. During
power-down, the slope of the falling voltage is set by the
200µA current source connected to ground and the exter-
nal GATE capacitor.
5V
SENSE
(Pin 16): 5V Current Limit Set Pin. With a sense
resistor placed in the supply path between 5V
IN
and
5V
SENSE
, the GATE pin voltage will be adjusted to maintain
a constant voltage across the sense resistor and a con-
stant current through the switch. A foldback feature makes
the current limit decrease as the voltage at the 5V
OUT
pin
approaches ground. To disable the current limit, 5V
SENSE
and 5V
IN
can be shorted together.
5V
IN
(Pin 17): 5V Supply Sense Input. Used to monitor the
5V input supply voltage. An undervoltage lockout circuit
prevents the switches from turning on when the voltage at
the 5V
IN
pin is less than 3.9V.
5V
OUT
(Pin 18): 5V Output Monitor. Used to monitor the
5V output supply voltage. The PWRGD signal cannot go
low until the 5V
OUT
pin exceeds 4.65V.
V
EEOUT
(Pin 19): –12V Supply Output. A 1.2 switch is
connected between V
EEIN
and V
EEOUT
. V
EEOUT
must
fall below –10.5V before the PWRGD signal can go low on
the LTC4241.
12V
OUT
(Pin 20): 12V Supply Output. A 0.5 switch is
connected between 12V
IN
and 12V
OUT
. 12V
OUT
must
exceed 11.1V before the PWRGD signal can go low on the
LTC4241
LTC4241
9
sn4241 4241f
BLOCK DIAGRA
W
+
+
+
+
+
+
+
+
+
+
3.9V
UVL
2.5V
UVL
+
+
REF
REF
REF
200µA
200µA
10µA
60µA
22µA
REF
PRIMARY CONTROL LOGIC
7
5
17 16 15 14 13 183
6
1 20
11
10
4 2 19
9V
UVL
8
9
12V
IN
12V
OUT
TIMER V
EEIN
V
EEOUT
5V
IN
5V
SENSE
GATE 3V
SENSE
3V
IN
12V
IN
12V
IN
3V
OUT
5V
OUT
GND
ON
PWRGD
FAULT
Q3
Q5
Q8
Q9
Q1
Q6
Q12
Q11
Q2
Q10
Q7
Q4
55mV
55mV
3V
OUT
5V
OUT
CP2
CP4 CP3
C
P1
PCI-BUS HOT SWAP
CONTROLLER
50mV
2.6V
UVL
8µs
FILTER
CHARGE
PUMP
12
AUXIN
AUXSENSE
AUXON
AUXILIARY
CONTROL
LOGIC
AUXGATE
AUXIN
3.3V AUXILIARY SUPPLY
HOT SWAP CONTROLLER
4241 BD
Z1
12V
Z2
20V
A1
A2
A3

LTC4241IGN#PBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Hot Swap Voltage Controllers PCI-Bus w/ 3.3V Auxiliary Hot Swap Cntr
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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