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NB4N7132DTR2G

P1-P3P4-P6
NB4N7132
http://onsemi.com
4
Table 5. DC CHARACTERISTICS V
DD
= 3.30 V $5%, GND = 0 V; T
A
= −40°C to +85°C
Symbol
Characteristic Min Typ Max Unit
V
DD
Power Supply Voltage, 3.30 V $5% 3.14 3.47 V
I
DD
Power Supply Current (Outputs open) 105 125 mA
P
D
Power Dissipation; Outputs Open; V
DD
= V
DDmax
450 mW
V
IN
Receiver Differential Voltage Amplitude; (IN, IN0, IN1), AC−Coupled,
Internally Biased to 1.2 V; Differential Measurement − (V
INn+
− V
INn−
) 300 2600
mV
V
OUT50
Output Differential Voltage Swing, peak−peak; (OUT, OUT0, OUT1)
Outputs loaded / terminated with 50 to V
DD
– 2.0 V
Differential Measurement − (V
OUTn+
− V
OUTn−
)
1000 2200
mV
V
OUT75
Output Differential Voltage Swing, peak−peak; (OUT, OUT0, OUT1)
Outputs loaded / terminated with 75 to V
DD
– 2.0 V
Differential Measurement − (V
OUTn+
− V
OUTn−
)
1200 2200
mV
LVCMOS/LVTTL INPUTS
V
IH
Input HIGH Voltage, TTL 2.0 V
DD
+ 0.5 V
V
IL
Input LOW Voltage, TTL 0 0.8 V
I
IH
Input HIGH Current, TTL; V
IN
= 2.4 V 100
A
I
IL
Input LOW Current, TTL; V
IN
= 0.5 V −100
A
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
Table 6. AC CHARACTERISTICS V
DD
= 3.3 V $5%, GND = 0 V −40°C to +85°C
Symbol Characteristic Min Typ Max Unit
f
IN
/
OUT
Input / Output Frequency Range 1.5 Gb/s
tr/tf Output rise and Fall Times (Note 3) 140 175 ps
t
PD
Propagation Delay, IN to OUT 0.375 4.0 ns
T
DJ
Deterministic Jitter Added to Serial Input Up to 1.5 Gb/s;
K28.5$ Pattern
40 ps pk−pk
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
3. Measured 20% to 80%
Figure 4. Timing Waveforms
IN1+/−
OUT+/−
IN0+/−
IN+/−
OUT0+/−
OUT1+/−
t
pd
t
pd
t
J
NB4N7132
http://onsemi.com
5
Figure 5. NB4N7132 Application Interface Example
NB4N7132 NB4N7132 SerDesSerDes
TX+
TX−
RX+
RX−
O1+
O1−
I1+
I1−
I+
I−
O+
O−
O+
O−
I+
I−
I1+
I1−
O1+
O1−
RX+
RX−
TX+
TX−
0.01F
0.01F
0.01F
0.01F
0.01F
0.01F
0.01F
0.01F
0.01F
0.01F
0.01F
0.01F
R
R
RT
RT RT RT
RT RT
“R” is 150 for both 100 differential or 150 differential traces.
“RT” matches the differential impedance of the link.
R
R
IN+/IN− Input Functionality
The differential inputs are internally biased to Y1.2 V. In
a typical application, the differential inputs are
capacitor−coupled and will swing symmetrically above and
below 1.2 V, preserving a 50% duty cycle to the outputs.
With this technique, the NB4N7132 will accept any
differential input allowing for LVPECL, CML, LVDS, and
HSTL input levels.
OUT+ / OUT− Outputs
The OUT+ and OUT− outputs of the NB4N7132 are
designed to drive differential transmission lines with
nominally 50 or 75 characteristic impedance. These
differential output buffers utilize positive emitter coupled
logic (PECL) architecture, but they do not require DC output
load resistors, and will operate properly with or without the
resistors.
OEx Output Enable
The NB4N7132 incorporates output enable pins, OE0 and
OE1, that work by powering down the output buffer and
associated driving circuitry. Using this approach results in
both differential outputs going HIGH, and a reduction in I
DD
current of approx. 29 mA for each disabled output pair.
When OEx is LOW, outputs are disabled, OUTx+ and
OUTx− are set HIGH.
Power Supply Bypass information
A clean power supply will optimize the performance of
the device. The NB4N7132 provides separate power supply
pins for the digital circuitry (V
DD
) and LVPECL outputs
(VDDPn). Placing a bypass capacitor of 0.01 F to 0.1 F
on each VDD pin will help ensure a noise free V
DD
power
supply. The purpose of this design technique is to try and
isolate the high switching noise of the digital outputs from
the relatively sensitive digital core logic.
Resource Reference of Application Notes
AND8002 − Marking and Date Codes
AND8009 − ECLinPS Plus Spice I/O Model Kit
ORDERING INFORMATION
Device Package Shipping
†
NB4N7132DTG TSSOP−28
(Pb−Free)
50 Units / Rail
NB4N7132DTR2G TSSOP−28
(Pb−Free)
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
NB4N7132
http://onsemi.com
6
PACKAGE DIMENSIONS
0.20 A
e
SECTION A−A
DETAIL A
(L1)
0.25
15
28
14
PIN ONE
LOCATION
NOTES:
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
2. DIMENSIONS IN MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE
0.08 MM TOTAL IN EXCESS OF THE “b”
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
4. DATUMS A AND B TO BE DETERMINED
AT DATUM PLANE H.
B
E
E1
BC
1
0.10
SEATING
A
C
D
C
PLANE
0.05
A
A2
A1
b
28X
0.10 ABC
A A
DETAIL A
DIM MIN MAX
MILLIMETERS
A −−− 1.20
A1 0.05 0.15
A2 0.80 1.05
b 0.19 0.30
b1 0.19 0.25
c 0.09 0.20
c1 0.09 0.16
D 9.60 9.80
E 6.40 BSC
E1 4.30 4.50
e 0.65 BSC
L 0.45 0.75
L1 1.00 REF
R 0.09 −−−
R1 0.09 −−−
S 0.20 −−−
01 0 8
02 12 REF
03 12 REF
_
_
__
L
03
01
R
R1
S
02
H
GAUGE PLANE
(b)
b1
c1
c
2X
28 LEAD TSSOP
DT SUFFIX
CASE 948AA−01
ISSUE O
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent
rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur.
Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries,
affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury
or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an
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PUBLICATION ORDERING INFORMATION
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5773−3850
NB4N7132/D
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
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Order Literature: http://www.onsemi.com/orderlit
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l
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NB4N7132DTR2G

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Buy NB4N7132DTR2G
Manufacturer:
ON Semiconductor
Description:
Communication ICs - Various 2.5 GBPS SER LNK REP
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