Si4708/09-B
Confidential Rev. 1.4 13
4. Functional Description
Figure 6. Si4708/09 FM Receiver Block Diagram
4.1. Overview
The Si4708/09 extends Silicon Laboratories Si4700 FM
tuner family, and further increases the ease and
attractiveness of adding FM radio reception to mobile
devices through small size and board area, minimum
component count, flexible programmability, and
superior, proven performance. Si4708/09 software is
backwards compatible to existing Si4700/01/02/03 FM
Tuner designs and leverages Silicon Laboratories'
highly successful and patented Si4700/01/02/03 FM
tuner. The Si4708/09 benefits from proven digital
integration and 100% CMOS process technology,
resulting in a completely integrated solution. It is the
industry's smallest footprint FM tuner IC requiring only
6.25 mm
2
board space and one external bypass
capacitor.
The device offers significant programmability, catering
to the subjective nature of FM listeners’ audio
preferences and variable FM broadcast environments
worldwide.
The Si4709 incorporates a digital processor for the
European Radio Data System (RDS) and the US Radio
Broadcast Data System (RBDS) including all required
symbol decoding, block synchronization, error
detection, and error correction functions.
RDS/RDBS* enables data such as station identification
and song name to be displayed to the user. The Si4709
offers a detailed RDS view and a standard view,
allowing adopters to selectively choose granularity of
RDS status, data, and block errors. Si4709 RDS
software is backwards compatible to the proven
Si4701/03, adopted by leading cell-phone and MP3
manufacturers world-wide.
The Si4708/09 is based on the superior, proven
performance of Silicon Laboratories' Aero architecture
offering unmatched interference rejection and leading
sensitivity. The device uses the same programming
interface as the Si4700/01/02/03 and supports multiple
bus modes. Power management is simplified with an
integrated regulator allowing direct connection to a 2.7
to 5.5 V battery for V
D
and 2.7 to 5.5 V battery for V
A
.
The Si4708/09 device’s high level of integration and
complete FM system production testing increases
quality to manufacturers, improves device yields, and
simplifies device manufacturing and final testing.
*Note: RDS/RBDS is referred to as RDS throughout the
remainder of this document.
4.2. FM Receiver
The Si4708/09 architecture and antenna design
increases system performance. To ensure proper
performance and operation, designers should refer to
the guidelines in "AN350: Si4708/09 Antenna,
Schematic, Layout, and Design Guidelines".
Conformance to these guidelines will help to ensure
excellent performance in weak signal, noisy, and
crowded signal environments where many strong
channels are present.
VIO
CONTROLLER
I
ADC
Q
ADC
Si4708/09
DSP
SCLK
SDIO
CONTROL
INTERFACE
SEN
DAC
DAC
ROUT
LOUT
0 / 90 LOW-IF
RSSI
TUNE
GPIO
AMPLIFIER
GPO
RST
RFGND
LNA
FMI
AFC
AGC
PGA
RCLK
REG
VA
VD
32.768 kHz
Headphone
Cable
RDS
(Si4709)
Si4708/09-B
14 Confidential Rev. 1.4
The Si4708/09’s patented digital low-IF architecture
reduces external components and eliminates the need
for factory adjustments. The receive (RX) section
integrates a low noise amplifier (LNA) supporting the
worldwide FM broadcast band (76 to 108 MHz). An
automatic gain control (AGC) circuit controls the gain of
the LNA to optimize sensitivity and rejection of strong
interferers.
An image-reject mixer downconverts the RF signal to
low-IF. The quadrature mixer output is amplified,
filtered, and digitized with high resolution
analog-to-digital converters (ADCs). This advanced
architecture achieves superior performance by using
digital signal processing (DSP) to perform channel
selection, FM demodulation, and stereo audio
processing compared to traditional analog
architectures.
4.3. General Purpose Output
The GPO pin can serve multiple functions. After
powerup of the device, the GPO pin can be used as a
general purpose input/output, and can be used as an
interrupt request pin for the seek/tune or RDS ready
functions. See register 04h, bits [3:2] in Section “6.
Register Descriptions” for information on GPO control. It
is recommended that the GPO pin not be used as an
interrupt request output until the powerup time has
completed (see Section “4.9. Reset, Powerup, and
Powerdown”). The GPO pin is powered from the V
IO
supply; therefore, general purpose input/output
functionality is available regardless of the state of the V
A
and V
D
supplies, or the ENABLE and DISABLE bits.
4.4. RDS/RBDS Processor and
Functionality
The Si4709 implements an RDS/RBDS processor for
symbol decoding, block synchronization, error
detection, and error correction. RDS functionality is
enabled by setting the RDS bit. The device offers two
RDS modes, a standard mode and a verbose mode.
The primary difference is increased visibility to RDS
block-error levels and synchronization status with
verbose mode.
Setting the RDS mode (RDSM) bit low places the
device in standard RDS mode (default). The device will
set the RDS ready (RDSR) bit for a minimum of 40 ms
when a valid RDS group has been received. Setting the
RDS interrupt enable (RDSIEN) bit and GPO[1:0] = 01
will configure GPO to pulse low for a minimum of 5 ms
when a valid RDS group has been received. If an invalid
group is received, RDSR will not be set and GPO will
not pulse low. In standard mode RDS synchronization
(RDSS) and block error rate A, B, C and D (BLERA,
BLERB, BLERC, and BLERD) are unused and will read
0. This mode is backward compatible with earlier
firmware revisions.
Setting the RDS mode bit high places the device in RDS
verbose mode. The device sets RDSS high when
synchronized and low when synchronization is lost. If
the device is synchronized, RDS ready (RDSR) will be
set for a minimum of 40 ms when a RDS group has
been received. Setting the RDS interrupt enable
(RDSIEN) bit and GPO[1:0] = 01 will configure GPO to
pulse low for a minimum of 5 ms if the device is
synchronized and an RDS group has been received.
BLERA, BLERB, BLERC and BLERD provide
block-error levels for the RDS group. The number of bit
errors in each block within the group is encoded as
follows: 00 = no errors, 01 = one to two errors, 10 =
three to five errors, 11 = six or more errors. Six or more
errors in a block indicate the block is uncorrectable and
should not be used.
4.5. Stereo Audio Processing
The output of the FM demodulator is a stereo
multiplexed (MPX) signal. The MPX standard was
developed in 1961 and is used worldwide. Today's MPX
signal format consists of left + right (L+R) audio, left –
right (L–R) audio, a 19 kHz pilot tone, and RDS/RBDS
data as shown in Figure 7.
Figure 7. MPX Signal Spectrum
The Si4708/09's integrated stereo decoder
automatically decodes the MPX signal. The 0 to 15 kHz
(L+R) signal is the mono output of the FM tuner. Stereo
is generated from the (L+R), (L-R), and a 19 kHz pilot
tone. The pilot tone is used as a reference to recover
the (L-R) signal. Separate left and right channels are
obtained by adding and subtracting the (L+R) and (L-R)
signals, respectively. The Si4709 uses frequency
information from the 19 kHz stereo pilot to recover the
57 kHz RDS/RBDS signal.
Adaptive noise suppression is employed to gradually
combine the stereo left and right audio channels to a
mono (L+R) audio signal as the signal quality degrades
0575338231915
Frequency (kHz)
Modulation Level
Stereo Audio
Left - Right
RDS/
RBDS
Mono Audio
Left + Right
Stereo
Pilot
Si4708/09-B
Confidential Rev. 1.4 15
to maintain optimum sound fidelity under varying
reception conditions. The signal level range over which
the stereo to mono blending occurs can be adjusted by
setting the BLNDADJ[1:0] register. Stereo/mono status
can be monitored with the ST register bit and mono
operation can be forced with the MONO register bit.
Pre-emphasis and de-emphasis is a technique used by
FM broadcasters to improve the signal-to-noise ratio of
FM receivers by reducing the effects of high frequency
interference and noise. When the FM signal is
transmitted, a pre-emphasis filter is applied to
accentuate the high audio frequencies. All FM receivers
incorporate a de-emphasis filter which attenuates high
frequencies to restore a flat frequency response. Two
time constants, 50 or 75 µs, are used in various regions.
The de-emphasis time constant is programmable with
the DE bit.
High-fidelity stereo digital-to-analog converters (DACs)
drive analog audio signals onto the LOUT and ROUT
pins. The audio output may be muted with the DMUTE
bit. Volume can be adjusted digitally with the
VOLUME[3:0] bits. The volume dynamic range can be
set to either –28 dBFS (default) or –58 dBFS by setting
VOLEXT=1.
The soft mute feature is available to attenuate the audio
outputs and minimize audible noise in very weak signal
conditions. The soft mute attack and decay rate can be
adjusted with the SMUTER[1:0] bits where 00 is the
fastest setting. The soft mute attenuation level can be
adjusted with the SMUTEA[1:0] bits where 00 is the
most attenuated. The soft mute disable (DSMUTE) bit
may be set high to disable this feature.
4.6. Tuning
The Si4708/09 uses Silicon Laboratories’ patented and
proven frequency synthesizer technology including a
completely integrated VCO. The frequency synthesizer
generates the quadrature local oscillator signal used to
downconvert the RF input to a low intermediate
frequency. The VCO frequency is locked to the
reference clock and adjusted with an automatic
frequency control (AFC) servo loop during reception.
The tuning frequency is defined as:
Channel spacing of 50, 100 or 200 KHz is selected with
bits SPACE[1:0]. The channel is selected with bits
CHAN[9:0]. The bottom of the band is set to 76 MHz or
87.5 MHz with the bits BAND[1:0]. The tuning operation
begins by setting the TUNE bit. After tuning completes,
the seek/tune complete (STC) bit will be set and the
RSSI level is available by reading bits RSSI[7:0]. The
TUNE bit must be set low after the STC bit is set high in
order to complete the tune operation and clear the STC
bit.
Seek tuning searches up or down for a channel with an
RSSI greater than or equal to the seek threshold set
with the SEEKTH[7:0] bits. In addition, an optional SNR
and/or impulse noise detector may be used to qualify
valid stations. The SKSNR[3:0] bits set the SNR
threshold required. The SKCNT[3:0] bits set the impulse
noise threshold. Using the extra seek qualifiers can
reduce false stops and, in combination with lowering the
RSSI seek threshold, increase the number of found
stations. The SNR and impulse noise detectors are
disabled by default.
Two seek modes are available. When the seek mode
(SKMODE) bit is low and a seek is initiated, the device
seeks through the band, wraps from one band edge to
the other, and continues seeking. If the seek operation
was unable to find a channel, the seek failure/band limit
(SF/BL) bit will be set high and the device will return to
the channel selected before the seek operation began.
When the SKMODE bit is high and a seek is initiated,
the device seeks through the band until the band limit is
reached and the SF/BL bit will be set high. A seek
operation is initiated by setting the SEEK and SEEKUP
bits. After the seek operation completes, the STC bit will
be set, and the RSSI level and tuned channel are
available by reading bits RSSI[7:0] and bits
READCHAN[9:0]. During a seek operation
READCHAN[9:0] is also updated and may be read to
determine seek progress. The STC bit will be set after
the seek operation completes. The channel is valid if the
seek operation completes and the SF/BL bit is set low.
At other times, such as before a seek operation or after
a seek completes and the SF/BL bit is set high, the
channel is valid if the AFC Rail (AFCRL) bit is set low
and the value of RSSI[7:0] is greater than or equal to
SEEKTH[7:0]. Note that if the AFCRL bit is set, the
audio output is muted as in the softmute case discussed
in Section “4.5. Stereo Audio Processing”. The SEEK bit
must be set low after the STC bit is set high in order to
complete the seek operation and clear the STC and
SF/BL bits. The seek operation may be aborted by
setting the SEEK bit low at any time.
The device can be configured to generate an interrupt
on GPO when a tune or seek operation completes.
Setting the seek/tune complete (STCIEN) bit and
GPO[1:0] = 01 will configure GPO for a 5 ms low
interrupt when the STC bit is set by the device.
For additional recommendations on optimizing the seek
function, consult "AN349: Si4708/09 Programming
Guide."
Freq (MHz) Spacing (kHz) Channel Bottom of Band (MHz)+=

SI4709-B-GM

Mfr. #:
Manufacturer:
Silicon Labs
Description:
RF RCVR FM 76MHZ-108MHZ 16QFN
Lifecycle:
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